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US 5,517,186 AGranted
EPROM-based crossbar switch with zero standby power
AssigneeAltera Corporation
InventorKerry Veenstra
Life of this patent
Estimating the term…
Abstract
An EPROM-based crossbar switch is disclosed that provides for the programmable interconnection of logic circuitry. Circuit layout and design features reduce circuit real estate and bitline parasitic capacitances, allowing a high level of integration and faster switching speeds.
Claims13
An electrically programmable EPROM-based programmable logic array switch for programmably interconnecting N input nodes to N output nodes comprising:
- a plurality of logic means each having a logic input connected to one of said input nodes for receiving a digital signal, each having a first logic output to which said digital signal is provided, and each having a second logic output to which an inverse of said digital signal is provided;
- a plurality of pairs of word lines, each pair of word lines being coupled to one of said input nodes through one of said logic means by connecting a first word line in each pair of word lines to said first logic output and connecting a second word line in each pair of word lines to said second logic output, said first and second word lines in each of said pairs of word lines receiving said digital signal and said inverse of said digital signal, respectively;
- a plurality of pairs of bit lines, each pair of bit lines having a first bit line and a second bit line on which there are first and second bit line signals, respectively, the second bit line signal being the inverse of the first bit line signal;
- a plurality of EPROM transistor pairs, each pair for programmably interconnecting one of said pairs of word lines to one of said pairs of bit lines, each EPROM transistor pair having a first EPROM transistor that has a first EPROM gate connected to said first word line in said one of said pairs of word lines, a first source connected to a supply having a predetermined potential, a first drain connected to said first bit line in said one of said pairs of bit lines, and a first floating gate, each EPROM transistor pair further having a second EPROM transistor that has a second EPROM gate connected to said second word line in said one of said pairs of word lines, a second source connected to said supply, a second drain connected to said second bit line in said one of said pairs of bit lines, and a second floating gate;
- and
- circuit means coupled between each of said pairs of bit lines and each of said N output nodes for providing each of said output nodes with output signals that are proportional to said first and second bit line signals, wherein, when a selected pair of EPROM transistors is erased by not applying charge to said first and second floating gates, said first and second transistors in said selected pair of EPROM transistors switch states in response to changes in said digital signal and changes in said inverse of said digital signal, respectively, such that said first and second bit line signals are proportional to said digital signal and said inverse of said digital signal, respectively, and wherein, when pairs of EPROM transistors other than said selected pair are programmed, by applying charge to said first and second floating gates, said first and second transistors in said pairs of EPROM transistors other than said selected pair do not switch states in response to changes in said digital signal and said inverse of said digital signal.
3 more elements
The apparatus of claim 5 wherein each of said circuit means further comprises a pair of cross-coupled inverters coupled to said pair of bit lines via said buffer transistors for limiting quiescent current flow in said pair of bit lines.
Programmable logic array integrated circuitry for electrically programmably connecting each of a plurality of input terminals to any respective one of a plurality of output terminals comprising:
- a plurality of pairs of word line conductors;
- a plurality of logic means for coupling said input terminals to said pairs of word line conductors, said input terminals being provided with input signals, wherein each of the logic means applies one of the input signals and a corresponding inverse input signal to respective ones of the word line conductors in an adjacent pair of word line conductors;
- a pair of bit line conductors coupled to each of said output terminals;
- means for programmably interconnecting each pair of word line conductors to each pair of bit line conductors consisting of a pair of programmable logic elements each having at least a first terminal and a second terminal, the first terminal of each programmable logic element being connected to a respective one of the word lines in one of the pairs of word line conductors, and the second terminal of each programmable logic element being connected to a respective one of the bit lines in that one of the pairs of bit line conductors, wherein the programmable logic elements can be selectively placed in one of two states:
- (a) a transmitting state, in which changes in the input signal and the inverse input signal produce changes in bit line signals on the bit line conductors, and (b) a blocking state, in which changes in the input signal and the inverse input signal do not produce changes in the bit line signals;
- and
- means for coupling the bit line conductors in each pair of bit line conductors to one of the output terminals.
4 more elements
Dependencies are inferred from the claim text.