Phase locked loop having digitally controlled oscillator and pulse signal generator

A frequency variable oscillator apparatus taking binary digital data consisting of upper data, consisting of a predetermined number of bits (M), as integer data, and lower data, consisting of a predetermined number of bits (N), as data after the radix point as input and outputting an oscillating signal made from a pulse row at a frequency corresponding to the binary digital data, said apparatus comprising:

• a selector row constructed from N selectors with each selector in the selector row being equipped with a select signal input terminal which takes a select signal as input and two data signal input terminals which take two data signals as input, with one of the two data signals inputted via the two data signal input terminals being selected to be outputted as a select output signal in accordance with the select signal inputted at the select signal input terminal, with the data signal for each bit of the lower N-bits of the binary digital data being inputted to one data signal input terminal of the respective selectors, with the data signal for the value "0" being inputted at the other data signal input terminal of the selector which receives the data signal for the least significant bit of the binary digital data and with the other data signal input terminal of any particular one of selectors exclusive of the selector which receives the data signal for the lowest significant bit of data taking as input the selector output signal from the selector which receives the data signal for a bit which is one bit lower in order than the data signal received by the particular selector;
• a counter, connected to each of the select signal input terminals for the selectors, for taking as input and counting the pulses of an external clock signal and outputting a count value as an N-bit digital value having a most significant bit and a least significant bit, with the counter providing the most significant bit, down to the least significant bit, of the data occurring in the count value to the select signal input terminals of the selectors in the order of the select signal input terminal of the selector which receives the data signal for the most significant bit, to the select signal input terminal for the selector which receives the data signal for the least significant bit, and with the select signal for each selector being periodically outputted in such a manner that the period for selecting a data signal for a corresponding bit is shorter for selectors which receive higher order data signals;
• a constant adder taking the upper M-bits of the binary digital data as input, adding 1 to the value expressing the upper M-bits and outputting the added upper M-bit data;
• a data selector taking as input the selector output signal from the selector output signals for the selectors in the selector row outputted from the row selector receiving the data signal for the most significant bit of the lower N-bits and selecting and outputting as selected data one of either the upper M-bit data inputted to the constant adder or the added upper M-bit data outputted from the constant adder in response to the inputted row selector output signal;
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• an oscillator for receiving the selected data outputted from the data selector, generating an oscillating signal (PO) at a period corresponding to the selected data and inputting part of the oscillating signal (PO) as the clock signal inputted to the counter.

A phase locked loop (PLL) apparatus, multiplying an inputted input pulse and outputting the multiplied input pulse as an output pulse in synchronization with the input pulse, said apparatus comprising:

• a selector row constructed from a predetermined number of selectors (N) with each selector in the selector row being equipped with a select signal input terminal which takes a select signal as input and two data signal input terminals which take two data signals as input from binary digital data having a plurality of bits including N least significant bits and M most significant bits, with one of the two data signals inputted via the two data signal input terminals being selected to be outputted as a select output signal in accordance with the select signal inputted at the select signal input terminal, with the data signal for each bit of the lower N-bits of the binary digital data being inputted to one data signal input terminal of a respective selector, with the data signal for the value "0" being inputted at the other data signal input terminal of the selector which receives the data signal for the least significant bit of the binary digital data and with the other data signal input terminal of any particular one of selectors exclusive of the selector which receives the data signal for the lowest significant bit of data taking as input the selector output signal from the selector which receives the data signal for a bit which is one bit lower in order than the data signal received by the particular selector;
• a counter, connected to each of the select signal input terminals for the selectors, for taking as input and counting the pulses of an external clock signal and outputting a count value as an N-bit digital value having a most significant bit and a least significant bit, with the counter providing the most significant bit, down to the least significant bit, of the data occurring in the count value to the select signal input terminals of the selectors in the order of the select signal input terminal of the selector which receives the data signal for the most significant bit, to the select signal input terminal for the selector which receives the data signal for the least significant bit, and with the select signal for each selector being periodically outputted in such a manner that the period for selecting a data signal for a corresponding bit is shorter for selectors which receive higher order data signals;
• a constant adder taking the upper M-bits of the binary digital data as input, adding 1 to the value expressing the upper M-bits and outputting the added upper M-bit data;
• a data selector taking as input the selector output signal from the selector output signals for the selectors in the selector row outputted from the row selector receiving the data signal for the most significant bit of the lower N-bits and selecting and outputting as selected data one of either the upper M-bit data inputted to the constant adder or the added upper M-bit data outputted from the constant adder in response to the inputted row selector output signal;
• an oscillator for receiving the selected data outputted from the data selector, generating an oscillating signal (PO) at a period corresponding to the selected data and outputting part of the oscillating signal (PO) as the clock signal to be inputted to the counter;
• a phase comparator for detecting the phase difference between a frequency divided signal being the oscillator signal outputted from the oscillator multiplied by 1/n and an externally inputted reference signal, n being a predetermined number;
• a control data generator for generating said binary digital data consisting of said M-bit data and N-bit data for making the phase difference detected by the phase comparator zero, and outputting the binary digital data as the N-bit data to be inputted to the selector row and the M-bit data inputted to the constant adder and the data selector circuit;
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• a downcounter for generating a borrow signal when the count value for the counter in the select signal generator becomes zero and capable of presetting data expressing the divider n using the borrow signal and an externally inputted preset signal, wherein the borrow signal outputted from the downcounter is outputted to the phase comparator as said frequency divided signal.

A phase locked loop (PLL) apparatus generating an output signal in phase synchronization with an externally inputted reference signal, said apparatus comprising:

• a multi-phase clock generating source for generating a plurality of clock signals having a prescribed phase difference as a time reference;
• a pulse phase-difference coder for coding the period of the reference signal and the phase difference between the reference signal and the output signal in time units corresponding to the phase difference between the multi-phase clocks outputted from the multi-phase clock generator source;
• data control means for generating frequency control data for phase synchronizing the reference signal and the output signal based on the reference signal period data coded at the pulse phase-difference coder and the phase difference data for the reference signal and the output signal;
• a digitally controlled oscillator for generating an oscillating signal corresponding to the frequency control data outputted from the data control means in time units corresponding to the phase difference between the multi-phase clocks outputted from the multi-phase clock generator source and outputting the oscillating signal externally as the output signal;
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• activation time control means for initially operating the pulse phase difference coder, presetting the reference signal period data obtained at the pulse phase encoder to the digitally controlled oscillator and then starting the generation of the digitally controlled oscillator oscillating signal at a timing prescribed by the reference signal at the time of activation of the apparatus.