Power supply isolation and switching circuit

#This invention relates to integrated circuit devices and, more particularly, to a power supply switching circuit formed in a semiconductor structure.

#Power supply switching circuits for providing power to electronic circuits or load devices are well known in the art. The switching circuit is coupled to primary and secondary power supply sources. The circuit compares the voltage of the primary power supply against a reference voltage, and switches the load to the secondary power supply when the primary supply voltage falls below the reference voltage.

#A typical application of the power supply switching circuit is in the area of portable electronic devices such as notebook computers. The computers generally have line voltage or a rechargeable battery as the primary power supply source. The secondary, power supply source is a back-up battery, such as a lithium battery, for providing power to the computer when the rechargeable battery voltage falls below an operation voltage level. The power supply switching circuit monitors the voltage level of the rechargeable battery and switches to the back-up battery widen the rechargeable battery sufficiently drains to fall below the reference voltage.

#FIG. 1 is a diagram of a known comparator circuit for comparing a primary power supply voltage to a reference voltage.

#FIG. 2 is a circuit diagram of a power supply switching circuit according to the prior art.

#FIG. 3 is a block diagram of a computer system having a dual power supply and switching circuit according to the present invention.

#FIG. 1 is a diagram of a prior art comparator circuit for comparing a primary power supply voltage to a reference voltage. A comparator 10 provides control signals to be used by a power supply switching circuit. One input 12 of the comparator 10 receives a primary power supply V.sub.cc, and the other input 14 receives a reference voltage V.sub.r. The output 18 of the comparator 10 is connected to an inverter 16 to generate an inverted output 20 of the comparator 10. The comparator 10 compares the voltage at the input 12 against the voltage at the input 14. When the voltage at the input 12 is greater than that of the input 14, the comparator 10 generates a logic high at its output 18, and the inverter 16 generates a logic low at the output 20. Conversely, when the voltage at the input 14 is greater than the voltage at the input 12, the comparator 10 generates a logic low at the output 18, and the inverter 16 generates a logic high at the output 20.

#FIG. 2 is a circuit diagram of a power supply switching circuit according to the prior art. The power supply switching circuit 22 comprises a pair of PMOS transistors 24 and 26. The PMOS transistor 24 is connected between a secondary power supply terminal V.sub.bat 32 and a load terminal 28. The PMOS transistor 26 is connected between the primary power supply terminal V.sub.cc 34 and the load terminal 28. In an integrated circuit of the N-well type, a parasitic diode 15 is formed by the P+ source region (not shown) and the N-well (not shown) of the transistor 24. In order to reverse bias the parasitic diode 15, the substrate of the transistor 24 is connected or biased to the load terminal 28, which is the highest voltage available in the switching circuit 22. In operation, when the primary power supply voltage V.sub.cc is greater than the reference voltage V.sub.r, the input 18 is at logic high and the input 20 is at logic low. The logic low signal at the input 20 turns on the transistor 26 and provides V.sub.cc to a load device 30 at the load terminal 28. In the meantime, the logic high signal at the input 18 turns off the transistor 24 and isolates V.sub.bat from the load terminal 28. For 5 volt load devices, the parasitic diode 15 is reversed biased since V.sub.cc is at 5 volts and V.sub.bat is at approximately 3-3.5 volts. When V.sub.cc falls below V.sub.r, the input 18 switches to a logic low and the input 20 switches to a logic high. The logic high signal at the input 20 turns off the transistor 26, and isolates V.sub.cc from the load device 30. The logic low signal at the input 18 turns on the transistor 24, and provides V.sub.bat to the load device 30.

#The problem recognized by the applicants is that when the load device 30 requires a 3 volt operating voltage and the secondary power supply V.sub.bat is above 3 volts, the parasitic diode 15 becomes forward biased and the current from the secondary power supply rapidly drains through the diode 15 and the terminal 34 of the primary power supply V.sub.cc until V.sub.bat falls to V.sub.cc. This leads to shorter life of the secondary power supply, and may even lead to a system failure of the load device 30. This occurs when the switching circuit 22 tries to switch to the secondary power supply when it had discharged below the minimum operating voltage of the load device 30.