Low current differential level shifter

A low current differential level shifter capable of stable frequency response and low current consumption over a wide range of supply voltage, comprising:

• a current switch which is controlled by a first voltage reference signal to generate a second differential voltage signal pair given a first differential voltage signal pair as input signals wherein providing the current switch with the first differential voltage signal pair improves noise immunity of the level shifter, thereby ensuring stable frequency response of the level shifter over a wide range of a supply voltage;
• a differential to single ended converter of the level shifter, having the second differential voltage signal pair as input signals, which performs a level shifter and gain function and which generates an output signal;
• and
• an output stage of the level shifter, having the output signal of the differential to single ended converter as an input signal, which generates a level shifter output signal wherein the output stage is controlled by the first voltage reference signal and a second voltage reference signal;
• wherein the first voltage reference signal and the second voltage reference signal are generated by a current source circuitry which comprises:
• a first MOS transistor having a first source/drain, a second source/drain, and a gate wherein the first source/drain of the first MOS transistor is electrically connected to the supply voltage;
• a second MOS transistor having a first source/drain, a second source/drain, and a gate wherein the first source/drain of the second MOS transistor is electrically connected to the supply voltage, the gate of the second MOS transistor is electrically connected to the gate of the first MOS transistor;
• a third MOS transistor having a first source/drain, a second source/drain, and a gate wherein the first source/drain of the third MOS transistor is electrically connected to the second source/drain of the first MOS transistor and the gate of the third MOS transistor;
• and
• a fourth MOS transistor having a first source/drain, a second source/drain, and a gate wherein the first source/drain of the fourth MOS transistor is electrically connected to the second source/drain of the second MOS transistor and the gates of the first MOS transistor and the second MOS transistor thereby defining a first node representative of the second voltage reference signal;
• and wherein the second source/drain of the fourth MOS transistor is electrically connected to the gate of the fourth MOS transistor, the gate of the third MOS transistor, the first source/drain of the third MOS transistor, and the second source/drain of the first MOS transistor thereby defining a second node representative of the first voltage reference signal.

A low current differential level shifter capable of stable frequency response and low current consumption over a wide range of supply voltage, comprising:

• a current switch which is controlled by a first voltage reference signal to generate a second differential voltage signal pair given a first differential voltage signal pair as input signals wherein providing the current switch with the first differential voltage signal pair improves noise immunity of the level shifter, thereby ensuring stable frequency response of the level shifter over a wide range of a supply voltage;
• a differential to single ended converter of the level shifter, having the second differential voltage signal pair as input signals, which performs a level shifter and gain function and which generates an output signal;
• and
• an output stage of the level shifter, having the output signal of the differential to single ended converter as an input signal, which generates a level shifter output signal wherein the output stage is controlled by the first voltage reference signal and a second voltage reference signal;
• wherein the current switch comprises:
• a first MOS transistor having a gate, a first source/drain, and a second source/drain;
• a second MOS transistor having a gate, a first source/drain, and a second source/drain;
• a third MOS transistor having a gate, a first source/drain, and a second source/drain;
• and a fourth MOS transistor having a gate, a first source/drain, and a second source/drain;
• a fifth MOS transistor having a gate, a first source/drain, and a second source/drain;
• a sixth MOS transistor having a gate, a first source/drain, and a second source/drain;
• a seventh MOS transistor having a gate, a first source/drain, and a second source/drain;
• wherein the first differential voltage signal pair is provided to the gates of the fifth MOS transistor and the sixth MOS transistor, respectively;
• the first reference voltage signal is provided to the gate of the seventh MOS transistor;
• wherein a first source/drain of the first MOS transistor, a first source/drain of the second MOS transistor, a first source/drain of the third MOS transistor, and a first source/drain of the fourth MOS transistor are electrically connected to the supply voltage;
• wherein a first signal of the second differential voltage signal pair is represented by a first node defined as the electrical connection of the gate of the first MOS transistor, the second source/drain of the second MOS transistor, the gate of the second MOS transistor, the first source/drain of the fifth MOS transistor, and the second source/drain of the fourth MOS transistor;
• wherein a second signal of the second differential voltage signal pair is represented by a second node defined as the electrical connection of the gate of the third MOS transistor, the second source/drain of the third MOS transistor, the gate of the fourth MOS transistor, the second source/drain of the first MOS transistor, and the first source/drain of the sixth MOS transistor;
• and
• wherein the second source/drain of the fifth MOS transistor is electrically connected to the second source/drain of the sixth MOS transistor and the first source/drain of the seventh MOS transistor;
• wherein the second source/drain of the seventh MOS transistor is electrically connected to a ground potential.

A low current differential level shifter capable of stable frequency response and low current consumption over a wide range of supply voltage, comprising:

• a current switch which is controlled by a first voltage reference signal to generate a second differential voltage signal pair given a first differential voltage signal pair as input signals wherein providing the current switch with the first differential voltage signal pair improves noise immunity of the level shifter, thereby ensuring stable frequency response of the level shifter over a wide range of a supply voltage;
• a differential to single ended converter of the level shifter, having the second differential voltage signal pair as input signals, which performs a level shifter and gain function and which generates an output signal;
• and
• an output stage of the level shifter, having the output signal of the differential to single ended converter as an input signal, which generates a level shifter output signal wherein the output stage is controlled by the first voltage reference signal and a second voltage reference signal;
• wherein the output stage comprises:
• a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor, with each MOS transistor having a gate, a first source/drain, and a second source/drain;
• wherein the first source/drains of the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are electrically connected to the supply voltage;
• the gates of the first MOS transistor, the second MOS transistor, and the third MOS transistor are supplied with the second voltage reference signal;
• and the second source/drain of the fourth MOS transistor is electrically connected to the first source/drain of the fifth MOS transistor;
• a sixth MOS transistor, a seventh MOS transistor, a eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor, with each MOS transistor having a gate, a first source/drain, and a second source/drain;
• wherein the second source/drains of the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the tenth MOS transistor are electrically connected to a ground potential;
• the gates of the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are supplied with the first voltage reference signal;
• a first inverter, a second inverter, and a third inverter;
• wherein the first inverter is supplied with the output signal of the differential to single ended converter as an input signal, the second inverter and the third inverter are supplied with an output signal of the first inverter;
• the first inverter is connected to the second source/drain of the first MOS transistor and the first source/drain of the sixth MOS transistor;
• the second inverter is connected to the second source/drain of the second MOS transistor and the first source/drain of the seventh MOS transistor;
• the third inverter is connected to the second source/drain of the third MOS transistor and the first source/drain of the eighth MOS transistor;
• wherein a first node representative of an output signal of the third inverter is defined as the electrical connection of the third inverter, the gate of the fourth MOS transistor, and the gate of the tenth MOS transistor;
• wherein a second node representative of an output signal of the second inverter is defined as the electrical connection of the second inverter, the gate of the fifth MOS transistor, and the gate of the ninth MOS transistor;
• wherein a third node representative of the level shifter output signal of the output stage is defined as the electrical connection of the second source/drain of the fifth MOS transistor, the first source/drain of the ninth MOS transistor, and a first capacitor;
• and
• wherein a fourth node is defined as the electrical connection of the second source/drain of the ninth MOS transistor, the first source/drain of the tenth MOS transistor, and a second capacitor.