Write precompensation circuit for compensating nonlinear magnetic effects in a recording channel

A write precompensation delay generator circuit comprising:

• a voltage controlled oscillator for producing a write current time period and differential ramp voltage, said differential ramp voltage providing first and second input signals;
• an early threshold circuit coupled to said first input signal, said early threshold circuit outputting a first output signal;
• a late threshold circuit coupled to said second input signal, said late threshold circuit outputting a second output signal;
• a comparator coupled to said first output signal and said second output signal, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal.

A write precompensation delay generator circuit comprising:

• an early threshold circuit coupled to a first input signal, said early threshold circuit outputting a first output signal;
• a late threshold circuit coupled to a second input signal, said late threshold circuit outputting a second output signal;
• a comparator coupled to said first output signal and said second output signal, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal;
• wherein said early threshold circuit includes a first resistor and said late threshold circuit includes a second resistor and wherein said output delayed data signal is dependent a ratio between said first and second resistors.

A write precompensation delay generator circuit comprising:

• an early threshold circuit coupled to a first input signal, said early threshold circuit outputting a first output signal;
• a late threshold circuit coupled to a second input signal, said late threshold circuit outputting a second output signal;
• a comparator coupled to said first output signal and said second output signal, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal;
• wherein said late threshold circuit is enabled in response to a write precompensation late enabling signal.

A write precompensation delay generator circuit comprising:

• an early threshold circuit coupled to a first input voltage, said early threshold circuit outputting an early threshold voltage, said early threshold voltage being a percentage of said first input voltage;
• a late threshold circuit coupled to a second input voltage, said late threshold circuit outputting a late threshold voltage, said late threshold voltage being a percentage of said second input voltage;
• a comparator coupled to said early threshold voltage and said late threshold voltage, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal;
• a voltage controlled oscillator for producing a write current time period and differential ramp voltage.

A write precompensation delay generator circuit comprising:

• an early threshold circuit coupled to a first input voltage, said early threshold circuit outputting an early threshold voltage, said early threshold voltage being a percentage of said first input voltage;
• a late threshold circuit coupled to a second input voltage, said late threshold circuit outputting a late threshold voltage, said late threshold voltage being a percentage of said second input voltage;
• a comparator coupled to said early threshold voltage and said late threshold voltage, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal;
• wherein said early threshold circuit includes a first resistor and said late threshold circuit includes a second resistor and wherein said output delayed data signal is dependent on a ratio between said first and second resistors.

A write precompensation delay generator circuit comprising:

• an early threshold circuit coupled to a first input voltage, said early threshold circuit outputting an early threshold voltage, said early threshold voltage being a percentage of said first input voltage;
• a late threshold circuit coupled to a second input voltage, said late threshold circuit outputting a late threshold voltage, said late threshold voltage being a percentage of said second input voltage;
• a comparator coupled to said early threshold voltage and said late threshold voltage, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal;
• wherein said late threshold circuit is enabled in response to a write precompensation late enabling signal.

A write precompensation delay generator circuit comprising:

• an early threshold circuit coupled to a first input voltage, said early threshold circuit outputting an early threshold voltage, said early threshold voltage being a percentage of said first input voltage;
• a late threshold circuit coupled to a second input voltage, said late threshold circuit outputting a late threshold voltage, said late threshold voltage being a percentage of said second input voltage;
• a comparator coupled to said early threshold voltage and said late threshold voltage, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal;
• wherein said percentage is a constant percentage.

A write precompensation delay generator circuit comprising:

• an early threshold circuit coupled to a first input voltage, said early threshold circuit outputting an early threshold voltage, said early threshold voltage being a percentage of said first input voltage;
• a late threshold circuit coupled to a second input voltage, said late threshold circuit outputting a late threshold voltage, said late threshold voltage being a percentage of said second input voltage;
• a comparator coupled to said early threshold voltage and said late threshold voltage, said comparator for identifying threshold voltage crossings and for providing an output delayed data signal;
• wherein a current source supplies a current to said early threshold circuit and to said late threshold circuit.