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US 5,517,145 AGranted
CMOS toggle flip-flop using adiabatic switching
AssigneeInternational Business Machines Corporation
InventorDavid J. Frank
Life of this patent
Estimating the term…
Abstract
A toggle flip-flop circuit is described incorporating eight bi-directional switches which may be dual rail wherein each bi-directional switch for each rail includes an n and p channel transistor coupled in parallel. Clock input signals may have rise and fall times longer than the RC time constant of a bi-directional switch and node capacitance being charged which dissipates, very low power across the switch. The invention provides a practical toggle flip-flop circuit using adiabatic switching for very low power dissipation.
Claims11
A low power toggle flip-flop comprising,
- three input terminals, CK1, CK1, and CK2,
- two output terminals, Q and QB,
- four switches,
- said second and fourth switches connecting Q to CK1 and CK1 respectively,
- said first and third switches connecting QB to CK1 and CK1 respectively,
- said first switch controlled by signals on Q and CK2 such that it is closed only when both the signal on Q is a logic 0 and the signal on CK2 is a logic 0,
- said second switch controlled by signals on QB and CK2 such that it is closed only when both the signal on QB is a logic 0 and the signal on CK2 is a logic 1,
- said third switch controlled by signals on Q and CK2 such that it is closed only when both the signal on Q is a logic 1 and the signal on CK2 is a logic 0,
- said fourth switch controlled by signals on QB and CK2 such that it is closed only when both the signal on QB is a logic 1 and the signal on CK2 is a logic 1.
6 more elements
A method for operating a low power toggle flip-flop with two input signals, CK1 and CK1, where CK1 is always the logic complement of CK1, and two output signals, Q and QB, comprising the following steps:
- (a) first, while CK1 is at logic 0, disconnecting one of CK1 and CK1 from Q, and connecting QB to one of CK1 and CK1 depending on whether Q=1 or =0, respectively,
- (b) second, ramping CK1 up to 1, thereby adiabatically charging QB to 1 if Q=1 or to 0 if Q=0,
- (c) third, disconnecting one of CK1 and CK1 from QB, and connecting Q to one of CK1 and CK1 depending on whether QB=1 or =0, respectively,
- (d) fourth, ramping CK1 back down to 0, thereby adiabatically charging Q to 0 if QB=1 or to 1 if QB=0 and
- wherein adiabatic charging includes using two more signals, CK2 and CK2, to control the connecting and disconnecting in steps (a) and (c).
2 more elements
A toggle flip-flop circuit comprising:
- first through eight dual-rail biodirectional switches,
- each dual-rail bi-directional switch including a first and second transmission gate,
- said first transmission gate including a p and n channel field effect transistor, the drain of the p channel field effect transistor and the source of the n channel field effect transistor coupled together at a first terminal and the source of the p channel field effect transistor and the drain of the n channel field effect transistor coupled together at a second terminal,
- said second transmission gate including a p and n channel field effect transistor, the drain of the p channel field effect transistor and the source of the n channel field effect transistor coupled together at a third terminal and the source of the p channel field effect transistor and the drain of the n channel field effect transistor coupled together at a fourth terminal,
- each dual-rail bi-directional switch having first and second control inputs, said first control input coupled to the gate of the n channel field effect transistor of said first and second transmission gates, said second control input coupled to the gate of the p channel field effect transistor of said first and second transmission gates,
- said first, second, fourth and third dual-rail bi-directional switches coupled in series in a dual-rail ring by interconnecting first and second terminals of respective switches corresponding to a first rail and by interconnecting third and fourth terminals of respective switches corresponding to a second rail,
- the interconnection between said fourth and third dual-rail bi-directional switches adapted for coupling said first rail to an input signal CK1 and said second rail to an input signal CK1, the interconnection between said first and second dual-rail bi-directional switches adapted for coupling said first rail to said input signal CK1 and said second rail to said input signal CK1,
- the second rail interconnection between said second and fourth dual-rail bi-directional switches connected to the control input of said fifth dual-rail bi-directional switch and provides an output signal Q and the first rail interconnection connected to the control input of said seventh dual-rail bi-directional switch and provides an output signal Q,
- the second rail interconnection between said first and third dual-rail bi-directional switches connected to the control input of said sixth dual-rail bi-directional switch and provides an output signal QB and the first rail interconnection connected to the control input of said eighth dual-rail bi-directional switch and provides an output signal QB,
- input signals CK2 and CK2 coupled through respective transmission gates of said eighth dual-rail bi-directional switch to said first and second control inputs of said fourth dual-rail bi-directional switch and through respective transmission gates of said sixth dual-rail bi-directional switch to said first and second control inputs of said second dual-rail bi-directional switch, and
- input signals CK2 and CK2 coupled through respective transmission gates of said seventh dual-rail bi-directional switch to said first and second control inputs of said third dual-rail bi-directional switch and through respective transmission gates of said fifth dual-rail bi-directional switch to said first and second control inputs of said first dual-rail bi-directional switch.
8 more elements
Dependencies are inferred from the claim text.