Synchronous self-timed clock pulse circuit having improved power-up performance

A self-timed synchronous clock circuit for generating a clock pulse from an external clock, the external clock having a first clock edge and first portion, and a second clock edge and a second portion, the clock circuit comprising:

• a first node;
• a first clock pulse generating circuit for generating a first clock pulse in response to the first edges of the external clock if said first node is at a first (normal) logic state, the first clock pulses having a first pulse edge and a second pulse edge, said first clock pulse generating circuit maintaining said first node at a second (lock-up) logic state in response to the first edges of the external clock if the first node is at the lock-up logic state;
• a reset circuit for changing said first node to the normal logic state in response to the second pulse edge;
• a sampling circuit for sampling said first node on the first clock edge of the external clock and holding the logic state for the remainder of the external clock cycle;
• and
• a lock-up correction circuit responsive to said sampling circuit for changing the logic state of the first pulse node to the normal logic state if the held logic state of the sampling circuit is the lock-up logic state, said lock-up correction circuit being disabled if the held logic state of the sampling circuit is the mormal logic state.