US 5,517,132 A · Logic synthesis method and semiconductor integrated circuit

Abstract

A semiconductor integrated circuit of registers and combinational logic circuits connected between the registers is generated by a top-down design technique. When performing the logic synthesizing of such a semiconductor integrated circuit by making use of data of register transfer level, a combinational logic circuit with a critical path is driven with power from a high-voltage source, a combinational logic circuit without a critical path is driven with power from a low-voltage source, and a level converter capable of converting an input signal of low voltage level into a high-voltage-level output is arranged in a register located upstream of a combinational logic circuit with a critical path. Compared with a technique in which only critical paths are driven with power from a high-voltage source, it becomes easier to determine where to arrange level converters. Additionally, the number of level converters required can be reduced, thereby facilitating design work. Each combinational logic circuit with a critical path is driven by the high-voltage source, so that the power consumption increases in comparison with a case where only critical paths are driven by the high-voltage source. However, the ratio of the number of combinational logic circuits with a critical path to the total number of combinational logic circuits contained in the whole semiconductor integrated circuit is negligible, and other combinational logic circuits without a critical path are driven by the low-voltage source. The entire power consumption of the semiconductor integrated circuit can be reduced.

Claims23

Dependent claims

A logic synthesis method for synthesizing, based on connection information of logic cells, a semiconductor integrated circuit of a plurality of registers and a plurality of combinational logic circuits connected between said registers, said logic synthesis method comprising:

a first step for mapping, when there exists among said plural combinational logic circuits a combinational logic circuit with a signal propagation delay time below a design delay upper limit, such a combinational logic circuit into a combinational logic circuit of a first type driven by a low-voltage source, and for mapping, when there exists among said plural combinational logic circuits a combinational logic circuit with a signal propagation delay time above the design delay upper limit, such a combinational logic circuit into a combinational logic circuit of a second type driven by a high-voltage source;
a second step for determining which of said combinational logic circuits of the first type outputs to a combinational logic circuit of the second type and for remapping a combinational logic circuit of the first type, determined to output to a combinational logic circuit of the second type, into the second-type;
and
a third step for determining which of said registers generates a signal to a combinational logic circuit of the second type, for mapping a register, determined to generate a signal to a combinational logic circuit of the second type, into a register driven by the high-voltage source, and for mapping a register, determined not to generate a signal to a combinational logic circuit of the second type, into a register driven by the low-voltage source.

1 more element

A semiconductor integrated circuit having a plurality of registers and a plurality of combinational logic circuits connected between said registers wherein:

part of said plural combinational logic circuits are formed by respective combinational logic circuits of a first type driven by a low-voltage source and the remaining part of said plural combinational logic circuits are formed by respective combinational logic circuits of a second type driven by a high-voltage source;
and
of said plural registers a register that has a combinational logic circuit of the first type on its input side and a combinational logic circuit of the second type on its output side is a circuit that has a temporary data storage driven by the low-voltage source and a level converter which is driven by the high-voltage source and which converts a low-voltage-level output signal, received from said temporary data storage, into a high-voltage-level output.

Dependencies are inferred from the claim text.

Logic synthesis method and semiconductor integrated circuit

Life of this patent

Logic synthesis method and semiconductor integrated circuit

Life of this patent

Abstract

Claims23