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US 5,517,131 AGranted
TTL input buffer with on-chip reference bias regulator and decoupling capacitor
AssigneeIntegrated Device Technology, Inc.
InventorsTa-Ke Tien, Chau-chin Wu, Richard C. Li
Life of this patent
Estimating the term…
Abstract
An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.
Claims8
An input buffer, comprising:
- a first PMOS transistor having a drain terminal, a source terminal receiving a positive power supply voltage, and a gate terminal coupled to receive an input signal;
- means for receiving a reference voltage which is insensitive to supply voltage fluctuations and for providing on an output lead a control voltage in accordance with said reference voltage;
- a second PMOS transistor having a drain terminal, a source terminal connected to said drain terminal of said first PMOS transistor, and a gate terminal coupled to receive said control voltage;
- and
- an NMOS transistor having a drain terminal connected to said drain terminal of said second PMOS transistor, a gate terminal coupled to receive said input signal, said drain terminal of said NMOS transistor providing an output signal of said input buffer.
2 more elements
A method for providing an input, buffer, comprising the steps of:
- providing a first PMOS transistor having a drain terminal, a source terminal receiving a positive power supply voltage, and a gate terminal coupled to receive an input signal;
- receiving a reference voltage which is insensitive to supply voltage variations and providing on an output lead a control voltage in accordance with said reference voltage;
- providing a second PMOS transistor having a drain terminal, a source terminal connected to said drain terminal of said first PMOS transistor, and a gate terminal coupled to receive said control voltage;
- and
- providing an NMOS transistor having a drain terminal connected to said drain terminal of said second PMOS transistor, a gate terminal coupled to receive said input signal, said drain terminal of said NMOS transistor providing an output signal of said input buffer.
2 more elements
Dependencies are inferred from the claim text.