Method and structure for reducing noise in output buffer circuits

An integrated circuit having a plurality of pull-down circuits, each said pull-down circuit being associated with an I/O lead of said integrated circuit, each said pull-down circuit comprising:

• a control signal terminal for receiving a control signal when said circuit is to operate to pull down its associated one of said I/O leads;
• a plurality of pull-down transistors having their current carrying terminals coupled between ground and said I/O lead, each of said pull-down transistors having a control terminal;
• a control circuit having:
• an input lead coupled to said control signal terminal;
• a plurality of driver transistors, each coupled for driving an associated one of said pull-down transistors;
• a plurality of series connected pass transistors, a first of said pass transistors coupled between said input lead and the control terminal of a first of said driver transistors, and subsequent ones of said pass transistors coupled between a preceding pass transistor and the control terminal of a subsequent one of said driver transistors, the control terminals of at least some of said pass transistors being connected to ground.

A method for controlling the slew rate of a signal provided on an output terminal comprising the steps of:

• providing a pull-down circuit coupled to said output terminal comprising:
• providing a control signal terminal for receiving a control signal when said circuit is to operate to pull down said output terminal;
• providing a plurality of pull-down transistors having their current carrying terminals coupled between ground and said output terminal, each of said pull-down transistors having a control terminal;
• and
• providing a control circuit having:
• an input lead coupled to said control signal terminal;
• a plurality of driver transistors, each coupled for driving an associated one of said pull-down transistors;
• and
• a plurality of series connected pass transistors, a first of said pass transistors coupled between said input lead and the control terminal of a first of said driver transistors, and subsequent ones of said pass transistors coupled between a preceding pass transistor and the control terminal of a subsequent one of said driver transistors, the control terminals of at least some of said pass transistors being connected to ground.