High-speed dual-buffered output circuit

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input to an input terminal thereof, said output circuit comprising:

• a first output buffer which is operatively connected to the input and the output terminals;
• a second output buffer which has a driving ability higher than a driving ability of said first output buffer and is operatively connected to the input terminal;
• means for generating a control signal during a predetermined period immediately after the input signal is input;
• and
• connection means for selectively connecting the output terminal to said second output buffer for the predetermined period in response to said control signal and in accordance with a signal level of the clock signal being high or low.

An output circuit for driving a load connected to an output terminal thereof in accordance with an input signal having positive-logic and negative-logic input signals, the input signals applied to an input terminal thereof, said output circuit comprising:

• a clock signal providing a control signal during a predetermined period after the input signal is input;
• a first output buffer operatively connected to the input and output terminals having first and second transistors connected in series between first and second power sources with a midpoint between said first and said second transistors as an output thereof, said first and said second transistors being responsive to the positive-logic and the negative-logic input signals, respectively;
• a second output buffer connected in parallel to said first output buffer and, when activated, operates with a driving ability higher than said first output buffer, said second output buffer having third and fourth transistors connected in series between the first and the second power sources with a midpoint between said third and said fourth transistors as an output thereof, said third and said fourth transistors each having ohmic resistance smaller than said first and said second transistors;
• activation means for selectively activating said second output buffer for the predetermined period in response to the control signal, said activation means having a fifth and sixth transistors, said fifth transistor being responsive to the clock signal and the positive-logic input signal and said sixth transistor being responsive to the clock signal and the negative-logic input signal;
• and
• said third and said fourth transistors being responsive to said fifth and said sixth transistors, respectively.

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input applied to an input terminal thereof, said output circuit comprising:

• a first output buffer which is operatively connected to the input and the output terminals;
• a second output buffer which is connected in parallel to said first output buffer and, when activated, operates with driving ability higher than said first output buffer;
• the clock signal providing a control signal during a predetermined period after the input signal is input;
• and
• activation means for selectively activating said second output buffer for the predetermined period in accordance with a signal level of the clock signal being high or low.

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input to an input terminal thereof, said output circuit comprising:

• a first output buffer which is operatively connected to the output terminal;
• a second output buffer which has driving ability higher than said first output buffer and is operatively connected to the input terminal;
• and
• connection means operating in accordance with a signal level of the clock signal being high or low for operatively connecting the output terminal to said second output buffer for a predetermined period when the input signal is input and, after the period, to said first output buffer.