Apparatus within an integrated circuit for automatically detecting a test mode of operation of the integrated circuit and selecting a test clock signal
AssigneeThomson Consumer Electronics, Inc.
InventorsDavid L. Albean, John W. Gyurek, Christopher D. Duncan
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Abstract
An integrated circuit (IC) includes circuitry for generating a clock signal during both a normal mode of operation and a test mode of operation. During the normal mode, an input clock signal is delayed via a skew corrector. In test mode, an input test clock signal bypasses the skew corrector via a clock signal source selector. The clock signal source selector is controlled automatically by a mode detector that responds to the input clock signals to determine the mode of operation of the IC.
Claims12
Signal selection apparatus included within an integrated circuit, said apparatus comprising:
- a first input terminal of said integrated circuit (IC) for receiving a first input signal comprising a periodic clock signal;
- a second input terminal of said IC for receiving a second input signal comprising a phase-shifted representation of said periodic clock signal during a first mode of operation of said IC;
- said second input signal being subject to a modification during a second mode of operation of said IC;
- means responsive to said first and said second input signals for generating first and second signals internal to said IC;
- means responsive to a control signal indicating whether said IC is in said first or said second mode of operation for coupling said first signal internal to said IC to a signal path during said first mode of operation and for coupling said second signal internal to said IC to said signal path during said second mode of operation;
- and
- means for detecting said modification of said second input signal during a first cycle of said periodic clock signal after said modification occurs and for generating said control signal indicating said second mode of operation during said first cycle of said periodic clock signal.
Signal selection apparatus included within an integrated circuit (IC), said apparatus comprising:
- a first input terminal of said integrated circuit for receiving a periodic sequence of binary pulses during first and second modes of operation of said IC;
- a second input terminal of said IC for receiving a second input signal comprising binary pulses exhibiting a predetermined timing relationship to said binary pulses received at said first input terminal during said first mode of operation and comprising a DC level during said second mode of operation;
- means included in said IC and responsive to said binary pulses received at said first input terminal during said first and second modes of operation for generating first and second binary pulse signals;
- means responsive to a first control signal for coupling said first binary pulse signal to a signal path in said IC during said first mode of operation, and for coupling said second binary pulse signal to said signal path during said second mode of operation;
- and
- means responsive to a second control signal indicating an initial mode of operation of said integrated circuit and to said DC level received at said second input terminal during said second mode of operation for generating said first control signal so that said second binary pulse signal is coupled to said signal path in said IC within a first period of said periodic sequence of binary pulses received at said first input terminal after said initial mode of operation ends when said initial mode of operation is followed by said second mode of operation.
Dependencies are inferred from the claim text.