Flip-flop circuit in a scanning test apparatus

A scanning method of testing a device, comprising the steps of:

• generating and transmitting an internal clock signal in a first clock signal generating section;
• generating and transmitting a second clock signal in a second clock signal generating section;
• latching scanning data in a first portion of a latch circuit in response to the internal clock signal at the time of a testing operation;
• and
• transmitting the latched scanning data to a second portion of the latch circuit in response to a sequencing of the second clock signal and the internal clock signal, said sequencing of the internal clock signal and the second clock signal being configured so that the latched scanning data is transferred from the first portion to the second portion after a predetermined time has passed since the scanning data were latched in the first portion.

A flip-flop circuit comprising:

• an internal clock signal generating section for generating an internal clock signal and for transmitting the generated internal clock signal;
• a data transferring clock signal generating section for generating a second clock signal and transmitting the second clock signal;
• and
• a latch section having a first stage connected to the internal clock signal generating section, the first stage of the latch section is configured to latch received scanning data in response to the internal clock signal transmitted at the time of a testing operation, and is configured to output the latched scanning data to a second stage of the latch section, the second stage is connected to the internal clock signal generating section and the data transferring clock generating section and is responsive to the internal clock signal to receive the latched scanning data and responsive to the second clock signal to latch the received latched scanning data in the second stage after a predetermined time has passed since the scanning data were latched in the first stage.