Stress released VLSI structure by the formation of porous intermetal layer

A porous intermetal dielectric layer, between layers of metallization in an integrated circuit, comprising:

• a first silicon oxide layer overlying a first layer of said layers of metallization;
• a spin-on-glass layer overlying said first silicon oxide layer wherein there are holes having a diameter of between about 0.2 and 0.5 micrometers within said spin-on-glass layer;
• and
• a second layer of silicon oxide overlying said spin-on-glass layer.

The stress-released integrated circuit comprising:

• at least a first patterned metallization layer over semiconductor device structures including gate electrodes and source and drain regions in and on a semiconductor substrate;
• a porous intermetal dielectric layer comprising:
• a first silicon oxide layer overlying said at least a first patterned metal layer;
• a spin-on-glass layer overlying said first silicon oxide layer wherein there are holes having a diameter of between about 0.2 and 0.5 micrometers within said spin-on-glass layer;
• and
• a second layer of silicon oxide overlying said spin-on-glass layer wherein said holes are not filled by said second silicon oxide layer;
• a second patterned metal layer contacting said at lease a first patterned metal layer in openings through said porous intermetal dielectric layer;
• and
• a top passivation layer wherein said holes within said intermetal dielectric layer release thermal stresses within said integrated circuit.