US 5,517,046 AGranted

High voltage lateral DMOS device with enhanced drift region

AssigneeMicrel, Inc.

InventorsMichael R. Hsing, Martin E. Garnett, James C. Moyer, Martin J. Alter, Helmuth R. Litfin

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Abstract

A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.

Claims20

Dependent claims

A lateral DMOS transistor structure comprising:

a semiconductor material of a first conductivity type, said semiconductor material having a first dopant concentration and a top surface;
a conductive gate overlying and insulated from said top surface of said semiconductor material;
a first region formed completely within said semiconductor material of said first conductivity type, said first region being self-aligned with said conductive gate when forming said first region, said first region being of said first conductivity type and having a second dopant concentration to form an enhanced drift region of said DMOS transistor, wherein said second dopant concentration is greater than said first dopant concentration;
a second region formed in said semiconductor material, said second region being of said first conductivity type and having a third dopant concentration greater than said second dopant concentration to form a drain region of said DMOS transistor, said second region contacting said first region, said second region being separated from said conductive gate by a first distance necessary to achieve a first breakdown voltage;
a third region formed in said semiconductor material, said third region being of a second conductivity type and having a fourth dopant concentration to form a body region of said DMOS transistor, said third region having a first end underlying said conductive gate, any remaining portion of said semiconductor material underlying said gate being of said first conductivity type;
and
a fourth region formed in said semiconductor material, said fourth region being of said first conductivity type and having said third dopant concentration to form a source region of said DMOS transistor, said fourth region being located within said third region,
wherein said first region acts to reduce an ON-resistance of said DMOS transistor as compared to said DMOS transistor lacking said first region.

5 more elements

A DMOS transistor formed as a cellular structure comprising:

a semiconductor material of a first conductivity type and a first dopant concentration, said semiconductor material having a top surface;
a conductive gate overlying and insulated from said top surface of said semiconductor material, said conductive gate forming a mesh having a plurality of substantially identical openings, each of said openings approximating an elongated diamond shape having a long diagonal and a short diagonal;
a plurality of first regions of said semiconductor material, said first regions being of said first conductivity type and a second dopant concentration to form substantially identical enhanced drift regions of said DMOS transistor, wherein said second dopant concentration is greater than said first dopant concentration;
a plurality of second regions of said semiconductor material, said second regions being of said first conductivity type and a third dopant concentration greater than said second dopant concentration to form substantially identical drain regions of said DMOS transistor, wherein each of said second regions contacts a respective one of said first regions, wherein each of said second regions is separated from said conductive gate by a first distance necessary to achieve a first breakdown voltage, and wherein each of said second regions underlies one of said openings in said mesh;
a plurality of third regions of said semiconductor material, said third regions being of a second conductivity type and a fourth dopant concentration to form substantially identical body regions of said DMOS transistor, each of said third regions having a first end, wherein said first end of each of said third regions underlies said conductive gate;
a plurality of fourth regions of said semiconductor material, each of said fourth regions being of said first conductivity type and of said third dopant concentration to form substantially identical source regions of said DMOS transistor, each of said fourth regions located within a respective one of said third regions, and wherein each of said fourth regions underlies one of said openings in said mesh;
a first conductive strip of material overlying and electrically contacting central portions of a first row of said source regions, said first conductive strip for being connected to a source voltage;
and
a second conductive strip of material overlying and electrically contacting central portions of a second row of drain regions adjacent to said first row of said source regions,
wherein said first regions act to reduce an ON-resistance of said DMOS transistor as compared to a DMOS transistor lacking said first region.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/384,168Filed 6 Feb 1995 · continuation in part
Priority: 19 Nov 1993
Granted: 14 May 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/65
Double-diffused metal-oxide semiconductor [DMOS] FETs: lateral dmos [ldmos] fets
H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 64/257
Source or drain electrodes for field-effect devices: for lateral devices wherein the source or drain electrodes are characterised by top-view…
H10D 64/519
Characterised by the conducting layers: characterised by their top-view geometrical layouts