Method and apparatus for asynchronous, bi-directional communication between first and second logic elements having a fixed priority arbitrator

A method for bi-directional communication between a first logic means having a first associated register and a second logic means having a second associated register, the first and second logic means operating asynchronously with respect to each other, the method comprising the steps of:

• transmitting in serial a first value from the first logic means to the first register, the first register having a first parallel connection to the second register for the transmission of values from the second register to the first register,
• transmitting an update signal from the first logic means to the first register to write the first value in parallel as a first input to a selector means, the selector means being coupled in parallel to the first parallel connection between the first and second registers for receiving as a second input values transmitted from the second register to the first register;
• transmitting the update signal from the first logic means to a synchronizer having as input a clock signal from the second logic means;
• synchronizing the update signal with the clock signal to produce as output from the synchronizer a synchronized update signal;
• transmitting the synchronized update signal from the synchronizer to the selector means, the selector means further having as input a write signal from the second logic means;
• selecting as output from the selector means one of the first input and the second input to the selector means in response to assertion of the update signal by the first logic means and assertion of the write signal by the second logic means, respectively;
• transmitting the output from the selector means in parallel to the second register;
• transmitting in parallel a second value from the second logic means to the second register to replace the first value in the second register with the second value;
• transmitting in parallel the second value in the second register to the first register upon assertion of a capture signal to the first register by the first logic means;
• and
• transmitting in serial the second value in the first register to the first logic means.

In a micro-controller integrated circuit (IC) having embedded memory and an in circuit emulator for imitating the behavior of the IC and executing debugging micro-code 14 stored in the embedded memory upon placing the IC in an interrogation mode, a method is provided for requesting a transition from normal operation of the IC to the interrogation mode and acknowledging from the micro-controller to an emulator control system disposed external to the IC that the transition has occurred, the method comprising the steps of:

• transmitting in serial a first value forming a transition request from the emulator system to a first register disposed within the IC, the first register having a first parallel connection to a second register for the transmission of values from the second register to the first register;
• transmitting an update signal from the emulator system to the first register to write the first value in parallel as a first input to a selector means, the selector means being coupled in parallel to the first parallel connection between the first and second registers for receiving as a second input values transmitted from the second register to the first register;
• transmitting the update signal from the emulator system to a synchronizer having as input a clock signal from the micro-controller;
• synchronizing the update signal with the clock signal to produce as output from the synchronizer a synchronized update signal;
• transmitting the synchronized update signal from the synchronizer to the selector means, the selector means further having as input a write signal from the micro-controller;
• selecting as output from the selector means one of the first input and the second input to the selector means in response to assertion of the update signal by the emulator system and assertion of the write signal by the micro-controller, respectively;
• transmitting the output from the selector means in parallel to the second register;
• transmitting in parallel a second value forming a transition acknowledgment from the micro-controller to the second register to replace the first value in the second register with the second value;
• transmitting in parallel the second value in the second register to the first register upon assertion of a capture signal to the first register by the emulator system;
• and
• transmitting in serial the second value in the first register to the emulator system.

An apparatus for enabling bi-directional communication between a first logic circuit and a second logic circuit operating asynchronously to each other, the apparatus comprising:

• a first register coupled to the first logic circuit;
• a second register coupled to the second logic circuit by a data bus, the first and second registers including corresponding pairs of bit cells for storing a first plurality of bits and a second plurality of bits, respectively, the first register receiving a current value stored in the second register in response to a capture signal from the first logic circuit;
• a synchronizer for synchronizing an update signal from the first logic circuit with a timing of the second logic circuit to generate a synchronized update signal;
• and
• a selector coupled to the first and second registers for receiving the first and the second plurality of bits, the selector providing a selector output corresponding to one of the first and second plurality of bits to the data bus in response to a write signal from the second logic circuit and the synchronized update signal.

A method for bi-directional communication between a first logic circuit having a first associated register and a second logic circuit having a second associated register, the first and second logic circuits operating asynchronously with respect to each other, the method comprising the steps of:

• a) transmitting from the first logic circuit to the second logic circuit by performing the steps of:
• i) serially transmitting a first value from the first logic circuit to the first register;
• ii) latching the first value in the first register in response to an update signal from the first logic circuit;
• iii) synchronizing the update signal with a clock signal from the second logic circuit to produce a synchronized update signal;
• iv) selecting a selected register from one of the first and second registers in accordance with the synchronized update signal and a write signal from the second logic circuit;
• and
• v) transmitting in parallel a selected value of the selected register to the second register and the second logic circuit in response to a read signal from the second logic circuit;
• b) transmitting from the second logic circuit to the first logic circuit by performing the steps of:
• i) transmitting in parallel a second value from the second logic circuit to the second register;
• ii) latching the second value from the second register into the first register in response to a capture signal from the first logic circuit;
• and
• iii) serially transmitting the second value in the first register to the first logic circuit.

A method for requesting a micro-controller to transition from a normal operating mode to an interrogation mode, comprising the steps of:

• serially transmitting a first value representing a transition request from an emulator to a first register, the micro-controller and the first register disposed within a same integrated circuit, the emulator located external to the integrated circuit, the first register coupled in parallel to a second register within the integrated circuit;
• transmitting an update signal from the emulator to the first register to latch the first value in the first register;
• generating a synchronized update signal from the update signal using a clock signal from the micro-controller;
• transmitting the synchronized update signal from the synchronizer to a selector for providing a selected value from one of the first and second registers;
• transmitting a write signal from the micro-controller to the selector;
• providing the selected value as an output of the selector in accordance with the synchronized update signal and the write signal;
• transmitting the output of the selector in parallel to the second register and the micro-controller;
• transmitting a second value representing a transition acknowledgment from the micro-controller to the second register to store the second value in the second register;
• latching the second value from the second register into the first register in response to a capture signal from the emulator;
• and
• serially transmitting the second value from the first register to the emulator.