Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count

A central processing unit comprising:

• A) first and second VLSI basic processing units (BPU)s for performing redundantly double precision data manipulations on data words to produce respectively a two data word result;
• B) a cache unit for receiving concurrently one data word from said first BPU and a second data word from the second BPU, said cache unit including means for storing data words including data words received concurrently from the first and second BPUs and for transferring concurrently two specified data words stored in the cache unit to both said first and second BPUs upon a request therefrom;
• C) first result holding means in said first BPU for holding one data word comprised of even numbered bits of the two data word result produced by a given double precision operation by the first BPU, said even numbered bits being divided into bytes;
• D) first parity generating means in said first BPU for generating a plurality of parity bits, one parity bit for each byte of said even numbered bits of a two data word result held in said first result holding means, said plurality of parity bits being included in the bytes held by the first result holding means;
• E) second result holding means in said second BPU for holding one data word comprised of odd numbered bits of the two data word result produced by the second BPU, said odd numbered bits being divided into bytes;
• F) second parity generating means in said second BPU for generating a plurality of parity bits, one parity bit for each byte of said odd numbered bits of a double data word result held in said second result holding means, said plurality of parity bits being included in the bytes held by the second result holding means;
• G) a first one data word wide result bus coupled to transfer one data word from the first result holding means of the first BPU to said cache unit;
• H) a second one data word wide result bus coupled to transfer one data word from second result holding means of the second BPU to said cache unit;
• I) first parity checking means in said cache unit for checking the parity of the bytes of a data word transferred from the first result holding means to the cache unit, and for issuing an error signal if a parity error is detected;
• J) second parity checking means in said cache unit for checking the parity of the bytes of a data word transferred from the second result holding means to the cache unit , and for issuing an error signal if a parity error is detected;
• K) first control circuit means in said first BPU for producing a first group and a second group of cache memory interface control signals for controlling transfer of data words between the first BPU and the cache unit, the first group of control signals for controlling the transfer of the data word held in the first result holding means, said first and second groups of control signals being divided into bytes;
• L) second control circuit means in said second BPU for producing a first group and a second group of cache memory interface control signals for controlling transfer of data words between the first BPU and the cache unit, the second group of control signals for controlling the transfer of the data word held in the second result holding means, said first and second groups of control signals being organized into bytes;
• M) third parity generating means in said first BPU for generating a parity bit for each byte of the first and second groups of control signals produced by the first control circuit means;
• O) fourth parity generating means in said second BPU for generating a parity bit for the first and second groups of control signals produced by the second control circuit means;
• P) first comparative circuit means in said first BPU to which is applied parity bits generated by said third parity generating means for the first group of control signals produced by the first control circuit means and parity bits generated by said fourth parity generating means for the first group of control signals produced by the second control circuit means for producing an error signal if said signals do not compare;
• Q) second comparative circuit means in said second BPU to which is applied parity bits generated by said fourth parity generating means for the second group of control signals produced by the second control circuit means and parity bits generated by said third parity generating means for the second group of control signals produced by the first control circuit means for producing an error signal if said signals do not compare;
• R) a double data word wide bus coupled for transferring concurrently two data words from said cache unit to said first and second BPUs;
• S) parity checking means in each of said first and second BPUs for parity checking data words received from said cache unit and for issuing an error signal if a parity error is detected;
• and
• T) control means responsive to an error signal issued by any of the parity checking means or comparative circuits means of said first and second BPUs and said cache unit, for taking a predetermined remedial action in response thereto.