Apparatus for detecting redundant circuit included in logic circuit and method therefor

A logic circuit optimizing apparatus for optimizing a logic circuit including a redundant circuit, comprising:

• first logic simulation executing means for executing logic simulation of said logic circuit using prescribed test data, said first logic simulation executing means generating first output data based on the prescribed test data applied to prescribed input nodes of the logic circuit;
• internal node selecting means for selecting one internal node in said logic circuit;
• pseudo fault setting means for setting a pseudo fault at the selected internal node in said logic circuit;
• second logic simulation executing means for executing logic simulation of said logic circuit including said pseudo fault, using said prescribed test data, said second logic simulation executing means generating second output data based on the same prescribed test data, which was used by the first logic simulation executing means, applied at the same prescribed input nodes of the logic circuit;
• coincidence detecting means for detecting the coincidence between said first and second output data;
• and
• deleting means for deleting a circuit portion as said redundant circuit which supplies an output signal to said internal node.

A method of detecting a redundant circuit in a logic circuit including said redundant circuit, comprising the steps of:

• executing logic simulation of said logic circuit using prescribed test data to generate first output data based on the prescribed test data applied to prescribed input nodes of the logic circuit;
• selecting one internal node in said logic circuit;
• setting a pseudo fault at the selected internal node in said logic circuit;
• executing logic simulation of said logic circuit including said pseudo fault using said prescribed test data to generate second output data based on the same prescribed test data, which was used to generate the first output data, applied at the same prescribed input nodes of the logic circuit;
• detecting the coincidence between said first and second output data;
• and
• processing said redundant circuit as connected to said internal node in response to coincidence between said first and second output data in said coincidence detecting step.

A method of optimizing a logic circuit including a redundant circuit, comprising the steps of:

• executing logic simulation of said logic circuit, using prescribed test data, to generate first output data based on the prescribed test data, applied to prescribed input nodes of the logic circuit;
• selecting one internal node in said logic circuit;
• setting a pseudo fault at the selected internal node in said logic circuit;
• executing logic simulation of said logic circuit including said pseudo fault, using said prescribed test data, to generate second output data based on the same prescribed test data, which was used to generate the first output data, applied at the same prescribed input nodes of the logic circuit;
• detecting the coincidence between said first and second output data;
• and
• deleting the circuit portion supplying an output signal to said internal node as said redundant circuit, in response to the coincidence detection.

A detecting apparatus for detecting the data of a redundant circuit by processing electronic data related to the design of a logic circuit including said redundant circuit, comprising:

• test data generating means for generating prescribed test data;
• logic simulation executing means for executing logic simulation of said logic circuit, using said prescribed test data applied to prescribed input nodes of the logic circuit, to output first output data indicating the result of the simulation;
• internal node selecting means for selecting one internal node in said logic circuit;
• pseudo fault setting means for setting a pseudo fault in the selected internal node;
• said logic simulation executing means executing logic simulation of said logic circuit including said pseudo fault, using the same prescribed test data, which was used to generate said first output data, applied at the same prescribed input nodes of the logic circuit to output second output data indicating the result of the simulation;
• and
• coincidence detecting means for detecting the coincidence between said first and second output data,
• the data of said redundant circuit being responsive to said coincidence detecting means to output data indicating that said redundant circuit is connected to said internal node.