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AssigneeMeridian Semiconductor, Inc.
InventorsGraham B. Whitted, III, Hsiao-Shih Chang, James A. Kane
Estimating the term…
An access control unit for a microprocessor receives fetch requests and operand access requests from a CPU of the microprocessor, and issues the requests to a bus/cache unit in a manner which reduces interference between fetch requests and operand access requests. Fetch addresses for fetch requests that cannot be immediately performed by the bus/cache unit are placed in a fetch address queue, allowing such fetch requests to be postponed. Operand access requests received by the access control unit are performed prior to postponed fetch requests. Thus, the execution unit of the CPU can continue to execute instructions which require operand accesses without waiting for pending fetch requests to be performed. Fetch requests that have been postponed by the access control unit are attempted on every clock cycle for which no operand access request is pending.
In a microprocessor in which a central processing unit (CPU) issues fetch requests and operand access requests to a bus unit to initiate accesses to memory, each of said fetch requests including a fetch address which specifies a starting memory location for fetching a block of code into an instruction buffer of said microprocessor, each of said operand access requests including an operand address which specifies a memory location for performing an operand access, an access control unit that postpones pending fetch requests issued by said CPU to allow subsequently-issued operand access requests from said CPU to be performed by said bus unit prior to said pending fetch requests, to thereby increase the performance of said microprocessor, said access control unit comprising:
In a microprocessor for which both code and operand data are stored in a common external memory, a fetch address queue that stores fetch addresses to allow corresponding fetch requests issued by a central processing unit (CPU) of said microprocessor to be postponed, said fetch requests specifying respective blocks of said code to be loaded into an instruction buffer of said microprocessor by a bus unit of said microprocessor, said fetch requests being postponed to permit operand access requests issued by said CPU to be performed by said bus unit prior to postponed fetch requests, said fetch addresses being held by said fetch address queue until said corresponding fetch requests are performed or canceled, said fetch address queue thereby allowing said CPU to access operand data without waiting for previously-issued fetch requests to be performed by said bus unit.
A method of processing fetch requests and operand access requests issued by a CPU of a microprocessor so as to give priority to pending operand access requests over pending fetch requests, said microprocessor comprising a memory unit which accesses a cache memory and an external memory in response to said fetch requests and said operand access requests, said method comprising the steps of:
In a microprocessor for which code and operand data are stored in a common external memory, and for which portions of said code and operand data are stored in a common cache memory of said microprocessor, a method of performing code fetches and operand accesses such that code fetches do not cause an unnecessary suspension of instruction execution, said method comprising the steps of:
Dependencies are inferred from the claim text.