US 5,515,507 AGranted

Multiple width data bus for a microsequencer bus controller system

AssigneeUnisys Corporation

InventorsLarry L. Byers, Joseba M. De Subijana, Wayne A. Michaelson, Lloyd E. Thorsbakken, Howard H. Tran

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Abstract

A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.

Claims34

Dependent claims

A system for generating and checking parity during transfer, in one of a plurality of data transfer word sizes, of data word signals between a data processor and a selected one of a plurality of logic circuits, said system comprising:

(a) data word size selection means, included in the data processor and the plurality of logic circuits, for selecting one of a plurality of data transfer word sizes for data word signals to be transferred;
(b) bus means, coupled to the data processor, the plurality of logic circuits, and said data word size selection means for selectively transferring data word signals and a first set of data word parity signals between the data processor and the plurality of logic circuits, said bus means transferring said data word signals in groupings of said selected data transfer word size;
(c) parity generation means, included in the data processor and the plurality of logic circuits and coupled to said bus means and said data word size selection means, for generating said first set of data word parity signals for said selected data word signals to be sent by said bus means;
and
(d) parity checking means, included in the data processor and the plurality of logic circuits and coupled to said bus means and said data word size selection means, for generating a second set of data word parity signals from said selected data word signals received from said bus means, for comparing said first set of data word parity signals received from said bus means with said second set of data word parity signals generated by said parity checking means, and for indicating a parity error if said first set of data word parity signals and said second set of data word parity signals exhibit a selected error condition.

2 more elements

A system for generating and checking parity during transfer, in one of a plurality of data word transfer sizes, of data word signals between a data processor and a selected one of a plurality of logic circuits, said system comprising:

(a) a data word size selection line, included in the data processor and the plurality of logic circuits for providing a selection signal indicative of a selected one of a plurality of data word transfer sizes for data word signals to be transferred, said selected data word transfer size modulo any other of the plurality of data word transfer sizes being non-zero;
(b) a bus coupled to the data processor, the plurality of logic circuits, and said data word size selection line, said bus selectively transferring data word signals in groupings of said selected data word transfer size;
(c) parity generation circuitry, included in the data processor and the plurality of logic circuits and coupled to said bus and said data word size selection line, for generating a first set of data word parity signals for said selected data word signals to be sent by said bus;
and
(d) parity checking circuitry, included in the data processor and the plurality of logic circuits and coupled to said bus and said data word size selection line, for generating a second set of data word parity signals from said selected data word signals received from said bus, comparing said first set of data word parity signals received from said bus with said second set of data word parity signals generated by said parity checking circuitry, and indicating a parity error if said first set of data word parity signals and said second set of data word parity signals exhibit a selected error condition.

2 more elements

A system for generating and checking parity during transfer of data word signals between processing units, said system comprising:

(a) data word size selection means included in the processing units for selecting one of two data word transfer sizes, said data word transfer sizes including words having a first number of bits per data transfer and words having a second number of bits per data transfer, said first number of bits modulo said second number of bits being non-zero;
(b) bus means coupled to the processing units and said data word size selection means for selectively transferring data word signals and a first set of data word parity signals between the processing units, said bus means transferring said data word signals in groupings of said selected data word transfer size;
(c) parity generation means, included in the processing units and coupled to said bus means and said data word size selection means, for generating said first set of data word parity signals for said selected data word signals to be sent by said bus means;
and
(d) parity checking means, included in the processing units and coupled to said bus means and said data word size selection means, for generating a second set of data word parity signals from said selected data word signals received from said bus means, for comparing said first set of data word parity signals received from said bus means with said second set of data word parity signals generated by said parity checking means, and for indicating a parity error if said first set of data word parity signals and said second set of data word parity signals exhibit a selected error condition.

2 more elements

A system for generating and checking parity during transfer, in either first or second data word transfer sizes, of data word signals between a data processor and a selected one of a plurality of logic circuits, the first data word transfer size modulo the second data word transfer size being non-zero, said system comprising:

(a) a data word size selection line, included in the data processor and the plurality of logic circuits for providing a selection signal indicative of a selected one of the first and second data word transfer sizes for data word signals to be transferred;
(b) a bi-directional bus coupled to the data processor, the plurality of logic circuits, and said data word size selection line, said bi-directional bus selectively transferring data word signals between the data processor and the plurality of logic circuits in groupings of said selected data word transfer size;
(c) parity generation circuitry, included in the data processor and the plurality of logic circuits and coupled to said bi-directional bus and said data word size selection line, to generate a first set of data word parity signals for said selected data word signals to be sent by said bi-directional bus, said first set of data word parity signals including two bits, one of said two bits representing a parity signal of a first selected half-word of said selected data word signals, the other of said two bits representing a parity signal of a second selected half-word of said selected data word signals, said parity generation circuitry including
(c1) data selection circuitry coupled to said data word size selection line to select ones of said data word signals for which parity signals are generated;
(c2) an output data register, coupled to said bi-directional bus and said data selection circuitry, to store said selected ones of said data word signals for subsequent transmission to said bi-directional bus;
(c3) a first output data parity line coupled to said bi-directional bus to send said parity signal of said first selected half-word of said selected data word signals;
(c4) a second output data parity line coupled to said bi-directional bus to send said parity signal of said second selected half-word of said selected data word signals;
(c5) first and second output data parity flip-flops, said first output data parity flip-flop coupled to said first output data parity line, said second output data parry flip-flop coupled to said second output data parity line;
(c6) first parity generation circuitry, coupled to said data selection circuitry and said first output data parity flip-flop, to generate said parity signal of said first selected half-word of said selected data word signals and to store said parity signal of said first selected half-word into said first output data parity flip-flop for subsequent transmission over said first output data line;
and
(c7) second parity generation circuitry, coupled to said data selection circuitry and said second output data parity flip-flop, to generate said parity signal of said second selected half-word of said selected data word signals and to store said parity signal of said second selected half-word into said second output data parity flip-flop for subsequent transmission over said second output data line;
and
(d) parity checking circuitry, included in the data processor and the plurality of logic circuits and coupled to said bi-directional bus and said data word size selection line, to generate a second set of data word parity signals from said selected data word signals received from said bi-directional bus, to compare said first set of data word parity signals received from said bi-directional bus with said second set of data word parity signals generated by said parity checking circuitry, and to indicate a parity error if said first set of data word parity signals and said second set of data word parity signals are different, said parity checking circuitry including
(d1) an input data register, coupled to said bi-directional bus, to store said selected word data signals received from said bi-directional bus;
(d2) a first input data parity line, coupled to said bi-directional bus, to receive said parity signal of said first selected half-word of said selected data word signals;
(d3) a second input data parity line, coupled to said bi-directional bus, to receive said parity signal of said second selected half-word of said selected data word signals;
(d4) first parity checking circuitry, coupled to said input data register and said first input data parity line, to check said parity signal of said first selected half-word of said selected data word signals and generate a first half-word parity error indication;
(d5) a half word mode indication line, coupled to said first parity checking circuitry, to indicate whether parity errors in said first selected half-word of said selected data word signals should be reported;
(d6) a first output parity error flip-flop, coupled to said first parity checking circuitry, to store said first half-word parity error indication if said half-word mode indication line indicates parity errors in said first selected half-word of said selected data word signals should be reported;
(d7) second parity checking circuitry, coupled to said input data register and said second input data parity line, to check said parity signal of said second selected half-word of said selected data word signals and generate a second half-word parity error indication;
and
(d8) a second output parity error flip-flop, coupled to said second parity checking circuitry, to store said second half-word parity error indication.

19 more elements

In a computer system having a bus connecting multiple processing units, the bus having a selectable data word transfer size, a method for generating and checking parity on data word signals transferred by the bus comprising the steps of:

(a) selecting a data word transfer size having a first number of bits per data word transfer or a second number of bits per data word transfer, said first number of bits modulo said second number of bits being non-zero;
(b) selecting data word signals to be transferred by the bus;
(c) generating a first parity signal from a first set of bits of said selected data word signals when said selected data word transfer size is said first number of bits per data word transfer;
(d) generating said first parity signal from a second set of bits of said selected data word signals when said selected data word transfer size is said second number of bits per data word transfer;
(e) generating a second parity signal frown a third set of bits of said selected data word signals when said selected data word transfer size is said first number of bits per data word transfer;
(f) generating said second parity signal from a fourth set of bits of said selected data word signals when said selected data word transfer size is said second number of bits per data word transfer;
(g) transferring said selected data word signals, said first parity signal, and said second parity signal over the bus;
(h) checking said first parity signal received from the bus with a parity signal generated from said first set of bits of said selected data word signals when said selected data word transfer size is said first number of bits per data word transfer and generating a first error indication if said first parity signal and said parity signal generated from said first set of bits are different;
(i) checking said first parity signal received from the bus with a parity signal generated from said second set of bits of said selected data word signals when said selected data word transfer size is said second number of bits per data word transfer and generating said first error indication if said first parity signal and said parity signal generated from said second set of bits are different;
(j) checking said second parity signal received from the bus with a parity signal generated from said third set of bits of said selected data word signals when said selected data word transfer size is said first number of bits and generating a second error indication if said second parity signal and said parity signal generated from said third set of bits are different;
and
(k) checking said second parry signal received from the bus with a parry signal generated from said fourth set of bits of said selected data word signals when said selected data word transfer size is said second number of bits and generating said second error indication if said second parity signal and said parity signal generated from said fourth set of bits are different.

9 more elements

In a computer system having a bus connecting multiple processing units, the bus having a selectable data word transfer size of words having 36 bits or words having 32 bits, a method for generating and checking parity on data word signals transferred by the bus, said method comprising the steps of:

(a) selecting a data word transfer size of 36 bits per data word transfer or 32 bits per data word transfer;
(b) selecting data word signals to be transferred by the bus;
(c) generating a first parity signal from bits zero through 17 of said selected data word signals when said selected data word transfer size is 36 bits;
(d) generating said first parity signal from bits 4 through 19 of said selected data word signals when said selected data word transfer size is 32 bits;
(e) generating a second parity signal from bits 18 through 35 of said selected data word signals when said selected data word transfer size is 36 bits;
(f) generating said second parity signal from bits 20 through 35 of said selected data word signals when said selected data word transfer size is 32 bits;
(g) transferring said selected data word signals, said first parity signal, and said second parity signal over the bus;
(h) checking said first parity signal received from the bus with a parity signal generated from bits zero through 17 of said selected data word signals when said selected data word transfer size is 36 bits and generating a first error indication if said first parity signal and said parity signal generated from bits zero through 17 are different;
(i) checking said first parity signal received from the bus with a parity signal generated from bits 4 through 19 of said selected data word signals when said selected data word transfer size is 32 bits and generating said first error indication if said first parity signal and said parity signal generated from bits 4 through 19 are different;
(j) checking said second parity signal received from the bus with a parity signal generated from bits 18 through 35 of said selected data word signals when said selected data word transfer size is 36 bits and generating a second error indication if said second parity signal anti said parity signal generated from bits 18 through 35 are different;
and
(k) checking said second parity signal received from the bus with a parity signal generated from bits 20 through 35 of said selected data word signals when said selected data word transfer size is 32 bits and generating said second error indication if said second parry signal and said parity signal generated from bits 20 through 35 are different.

9 more elements

Dependencies are inferred from the claim text.

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Abstract