Apparatus and method for clock alignment and switching

In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals and switching therebetween, comprising:

• a selecting and switching circuitry for receiving said first and second redundant timing signals and designating one of said redundant timing signals as ACTIVE and the other as INACTIVE, and providing said ACTIVE timing signal as an output timing reference signal, said selecting and switching circuitry further switching said ACTIVE and INACTIVE timing signal designation and said output timing reference signal in response to receiving a loss of frame loss of clock, or a clock switching signal;
• a first delay path having a programmable delay value coupled to said selecting circuitry, receiving said ACTIVE redundant timing signal and producing a first output timing signal;
• a second delay path having a programmable delay value coupled to said selecting circuitry, receiving said INACTIVE redundant timing signal and producing a second output timing signal;
• a phase detector coupled to said first and second delay paths, receiving said ACTIVE and INACTIVE output timing signals, and generating a status signal indicative of phase relationship therebetween;
• a temperature compensation circuit coupled to said first and second delay paths and measuring an effect of temperature change on said delay paths;
• a controller coupled to said phase detector for controlling said programmable delay values of said first and second delay paths to phase align said output timing signals in response to said status signal, and further coupled to said temperature compensation circuit for adjusting said programmable delay values in response to said measured effect of temperature change on said delay paths.

A method for aligning and switching between first and second redundant timing signals, comprising the steps of:

• selecting one of said first and second timing signals as an ACTIVE timing signal and the other as an INACTIVE timing signal, and providing said ACTIVE timing signal as an output timing reference;
• detecting a phase relationship of said ACTIVE and INACTIVE timing signals;
• incrementally delaying said INACTIVE timing signal until said detected phase relationship of said INACTIVE timing signal and said ACTIVE timing signal is in phase alignment;
• and
• switching said ACTIVE and INACTIVE timing signal designation and said output timing reference signal in response to receiving a loss of frame or loss of clock signal for said ACTIVE timing signal or a clock switching command.

An integrated circuit for aligning and switching a first and second redundant timing reference signals, comprising:

• circuitry for selecting from said first and second redundant timing reference signals an active timing reference;
• a first delay pipeline receiving said first redundant timing reference signal, delaying said first redundant timing signal by a first programmable delay amount, and generating a first internal reference timing signal;
• a second delay pipeline receiving said second redundant timing reference signal, delaying said second redundant timing signal by a second programmable delay amount, and generating a second internal reference timing signal;
• a first phase detector coupled to said first delay pipeline and generating a first set of delay pipeline control signals in response to a phase relationship between said active timing reference and said first internal reference timing signal if said second redundant timing reference is designated as said active timing reference, and said first delay pipeline delaying said first redundant timing reference in response to said delay pipeline control signals;
• a second phase detector coupled to said second delay pipeline and generating a second set of delay pipeline control signals in response to a phase relationship between said active timing reference and said second internal reference timing signal if said first redundant timing reference is designated as said active timing reference, and said second delay pipeline delaying said second redundant timing reference in response to said delay pipeline control signals;
• and
• circuitry for switching said active timing reference between said first and second redundant timing reference signals in response to receiving a clock switching command or a loss of frame or loss of clock signal.