Transmission circuit for transmitting fixed-length data

A transmission circuit for transmitting a first type of fixed-length data and a second type of fixed-length data via a communication line, said second type of fixed-length data being transferred to fill time slots in the communication line at which there is no first type of fixed-length data to be transmitted, each of said first and second types of fixed-length data including first data, second data and third data, the first, second and third data of said first fixed-length data respectively indicating a destination, an error correcting code of the first data and desired information, the first and second data of said second type of fixed-length data having predetermined bit patterns and the third data of said second type of fixed-length data having any arbitrary bit pattern, said transmission circuit comprising:

• first output means for generating and outputting the first data of said first type of fixed-length data;
• second output means for generating and outputting data having a predetermined bit pattern, the data output from said second output means being used as the third data of said second type of fixed-length data;
• pre-selecting means, coupled to said first output means and second output means, for selecting an output of one of said first and second output means;
• error correcting code generating means, coupled to said pre-selecting means, for generating the second data of said first type of fixed-length data based on the first data of said first type of fixed-length data supplied from said first output means via said pre-selecting means;
• third output means for generating and outputting the first and second data of said second type of fixed-length data;
• scrambler means, coupled to said pre-selecting means, for scrambling data supplied from said first and second output means via said pre-selecting means;
• and
• a single selecting means, coupled between said pre-selecting means, said error correcting code generating means, said third output means and said scrambler means to receive directly all outputs thereof, and an output terminal of said transmission circuit, for selecting an output of one of said pre-selecting means, said error correcting code generating means, said third output means and said scrambler means, wherein, due to selecting operations of said preselecting means and said selecting means, said first type of fixed length data and said second type of fixed-length data are output from said selecting means,
• said selecting means including n identical circuits arranged in parallel, n being an integer corresponding to the number of bits in data being transmitted, each of said circuits including four NAND gates each having a first input receiving a control signal and a second input receiving a bit of an output of the respective one of said pre-selecting means, said error correcting code generating means, said third output means and said scrambler means, respectively, an OR gate which is coupled to and receives all outputs of said four NAND gates, and a D-type flip flop receiving an output of said OR gate and outputting said first type of fixed length data and said second type of fixed-data at said output terminal.

A transmission circuit for transmitting a first type of fixed-length data and a second type of fixed-length data via a communication line, said second type of fixed length data being transmitted to fill time slots in the communication line at which there is no first type of fixed-length data to be transmitted, each of said first and second types of fixed-length data including first data, second data and third data, the first, second and third data of said first fixed-length data respectively indicating a destination, an error correcting code of the first data and desired information, the first and second data of said second type of fixed-length data having predetermined bit patterns and the third data of said second type of fixed length data having any arbitrary bit pattern, said transmission circuit comprising:

• first output means for generating and outputting the first data of said first type of fixed-length data;
• second output means for generating and outputting data having a predetermined bit pattern, the data output from said second output means being used as the first and second and third data of said second type of fixed-length data;
• pre-selecting means, coupled to said first output means and second output means, for selecting an output of one of said first and second output means;
• error correcting code generating marts, coupled to said pre-selecting means, for generating the second data of said first type of fixed-length data based on the first data of said first type of fixed length data supplied from said first output means via said pre-selecting means;
• scrambler means, coupled to said pre-selecting means, for scrambling data supplied from said first and second output means via said pre-selecting means;
• control means coupled to said pre-selecting means, said error correcting code generating means and said scrambler and generating a select signal;
• and
• a single selecting means, connected to said control means and also coupled between said preselecting means, said error correcting code generating means and said scrambler means to receive directly all outputs thereof, and an output terminal of said transmission circuit, for selecting, in response to said select signal, an output of one of said pre-selecting means, said error correcting code generating means and said scrambler means, wherein, due to selecting operations of said pre-selecting selecting means, said first type of fixed-length data and said second type of fixed-length data are output from said selecting means at said output terminal.