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AssigneeInternational Business Machines Corporation
InventorEdward E. Horton, III
Estimating the term…
A complete fail signature for an integrated circuit is compared to at least one predicted fail signature generated using a hardware fault simulator to generate fault candidates for the integrated circuit representing the most likely faults present within the tested circuit or device. The complete fail signature may be generated by obtaining physical test data for the integrated circuit derived by testing the integrated circuit using test vectors and comparing the results of the testing with the test results of a flawless integrated circuit to generate a fail signature. Also, the complete fail signature may be generated by compiling the logic of the integrated circuit into binary language suitable for simulation in a hardware fault simulator and compiling the test vectors into binary language suitable for simulation in the hardware fault simulator. The logic function of the integrated circuit may be simulated on the hardware fault simulator and the test vectors applied to the hardware fault simulator to determine an expected output of the integrated circuit. The expected output may be combined with the fail signature to generate a complete fail signature representative of a complete output pattern of the integrated circuit.
A method for diagnosing faults in an application specific integrated circuit comprising:
A method of diagnosing faults in an application specific integrated circuit comprising:
A system for diagnosing faults in an application specific integrated circuit comprising:
A system of diagnosing faults in an application specific integrated circuit comprising:
Dependencies are inferred from the claim text.