Process for testing the operation of an application specific integrated circuit and application specific integrated circuit relating thereto

An application specific integrated circuit formed on a single silicon chip, comprising:

• application-dependent devices which are dependent on the application of the integrated circuit;
• a standardized central :processing unit having a plurality of input/output gateways that are coupled to the application-dependent devices for interfacing the standardized central processing unit with the application-dependent devices during operation of the application specific integrated circuit,
• at least one shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to inject onto its respective line a value entered serially through the at least one shift register and being able to sample the value of the binary signal carried by its respective line with a view to a reading of this value through the at least one shift register;
• and
• wherein the elementary cells of the at least one shift register are mounted between the standardized central processing unit and the application-dependent devices on lines corresponding to the input/output gateways of the standardized central processing unit.

A process for testing the operation of an application specific integrated circuit formed on a single silicon chip, the application specific integrated circuit including a standardized processor and at least one application-dependent circuit, the standardized processor having a plurality of input/output lines for interfacing with the at least one application-dependent circuit, the process including the steps of:

• A. forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements mounted between the standardized processor and the at least one application-dependent circuit, the serial scan path further including a respective scan path element mounted on each of the plurality of input/output lines for interfacing the standardized processor with the at least one application-dependent circuit;
• B. executing a test program on the standardized processor in the application specific integrated circuit, the test program generating test results on at least some of the input/output lines of the standardized processor;
• and
• C. reading the test results through the serial scan path.

An application specific integrated circuit formed on a single silicon chip, comprising:

• a standardized processor;
• at least one application-dependent circuit which is dependent on the application of the integrated circuit and which is connected to the standardized processor, the standardized processor having a plurality of input/output lines for interfacing with the at least one application-dependent circuit;
• and
• at least one serial shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to output onto its respective line a value entered serially through the at least one serial shift register, each cell further being able to sample the value of a binary signal carried by its respective line so that binary signals on the lines on which the set of elementary cells is mounted can be read through the at least one serial shift register;
• and
• wherein elementary cells of the at least one serial shift register are mounted between the standardized processor and the at least one application-dependent circuit on the input/output lines of the standardized processor that interface with the at least one application-dependent circuit.

A process for testing the operation of an application specific integrated circuit formed on a single silicon chip, the application specific integrated circuit including a processor and a plurality of application-dependent circuits, the application specific integrated circuit having a plurality of internal connection lines for interfacing between the application-dependent circuits and for further interfacing between the processor and the plurality of application-dependent circuits, the process including the steps of:

• forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements, each scan path element being mounted on a respective connection line;
• entering test data through the serial scan path, the test data being characteristic of at least one of the plurality of application-dependent circuits;
• storing the test data within the application specific integrated circuit;
• executing a test program on the processor in the application specific integrated circuit that reads the test data and performs a processing operation on at least a portion of the test data;
• storing test results of the processing operation in the application specific integrated circuit;
• and
• reading the stored test results from the application specific integrated circuit.

A process for testing the operation of an application specific integrated circuit, the application specific integrated circuit including a processor and a plurality of application-dependent circuits, the application specific integrated circuit having a plurality of internal connection lines for interfacing between the application-dependent circuits and for further interfacing between the processor and the plurality of application-dependent circuits, the application specific integrated circuit further including a program memory for storing an application program for execution by the processor, the process including the steps of:

• forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements, each scan path element being mounted on a respective connection line;
• controlling the serial scan chain to input a verification address;
• storing the verification address within the application specific integrated circuit;
• executing the application program until the address of the program memory equals the verification address;
• and
• reading a value present on at least one connection line of the processor out of the application specific integrated circuit.

A process for testing the operation of an application specific integrated circuit, the application specific integrated circuit including a processor and a plurality of application-dependent circuits, the application specific integrated circuit having a plurality of internal connection lines for interfacing between the application-dependent circuits and for further interfacing between the processor and the plurality of application-dependent circuits, the application specific integrated circuit further including a program memory for storing an application program for execution by the processor, the process including the steps of:

• forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements, each scan path element being mounted on a respective connection line;
• determining a program memory failure address at which the application program fails;
• starting execution of the application program;
• halting execution of the application program at the determined failure address;
• entering expected data through the serial scan chain so that the plurality of connection lines interfacing the processor to the plurality of application-dependent circuits include values equaling those that would be expected if the application program were to execute without failure;
• and
• re-starting execution of the application program.

An application specific integrated circuit formed on a single silicon chip, comprising:

• a standardized processor having a plurality of input/output lines;
• at least one application-dependent device which is dependent on the application of the integrated circuit and is connected to at least one of the input/output lines of the standardized processor;
• and
• a standardized shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to inject onto its respective line a value entered serially through the standardized shift register and being able to sample the value of the binary signal carried by its respective line so that the value can be read through the standardized shift register;
• wherein an elementary cell of the standardized shift register is mounted between the standardized processor and the at least one application-dependent device on each of the at least one input/output line of the standardized processor that is connected to the application-dependent device.

An application specific integrated circuit formed on a single silicon chip, comprising:

• a standardized device having a plurality of input/output lines;
• at least one application-dependent device which is dependent on the application of the integrated circuit and is connected to at least one of the input/output lines of the standardized device;
• and
• a shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to inject onto its respective line a value entered serially through the shift register and being able to sample the value of the binary signal carried by its respective line so that the value can be read through the shift register;
• wherein an elementary cell of the shift register is mounted between the standardized device and the at least one application-dependent device on each of the at least one input/output line of the standardized device that is connected to the application-dependent device.