Reducing errors in digital communication
AssigneeAdvanced Techcom, Inc.
InventorAdolf J. Giger
Life of this patent
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Abstract
Errors in communication of a bit stream of information are reduced by incorporating an error checking facility (e.g., parity checking bits) in the information, sending the information on two independent communication channels, and selecting the information sent on one or the other of the two channels based on an error checking analysis of the information sent on both of the channels.
Claims20
A method for reducing bit errors in communication of a stream of digital information comprising
- incorporating an error checking facility in the information,
- sending the information on two independent communication channels, and
- selecting the information sent on one or the other of the two channels based on an error checking analysis of the information sent on both of the channels.
The method of claim 7 wherein the two channels impose different delays on the communication of the information and the method further comprises compensating for the different delays prior to the selecting step.
A method for reducing bit errors in communication of a stream of digital information comprising
- organizing the information in blocks of bits, incorporating error correcting information in each of the blocks of bits,
- sending the information on two independent communication channels imposing different delays on the communication of the information,
- compensating for the different delays to synchronize the information sent on the two channels,
- selecting the synchronized information sent on one or the other of the two channels by determining a relative degree of error exhibited in the information sent on the two channels, and
- repeating the organizing, incorporating, sending step, compensating step, and selecting steps for the information selected in the selecting step.
Digital communication apparatus for reducing bit errors in communication of a stream of digital information, comprising one or more connected systems, each system having
- a processor incorporating an error checking facility in the information,
- two independent communication channels,
- a transmitter sending the information incorporating the error checking facility on the two independent communication channels,
- a receiver receiving the information sent on the two communication channels, and
- a controller selecting the information received on one or the other of the two channels based on an error checking analysis of the information sent on both of the channels.
Digital communication apparatus for reducing bit errors in communication of a stream of digital information, comprising two or more connected systems, each system having
- a processor organizing the information in blocks of bits and incorporating error correcting information in each of the blocks of bits,
- two independent communication channels imposing different delays on the communication of the information,
- a transmitter sending the information incorporating the error checking facility on the two independent communication channels,
- a receiver receiving the information sent on the two communication channels,
- a synchronizer compensating for the different delays imposed by the two channels, and
- a controller selecting the synchronized information received on one or the other of the two channels by determining a relative degree of error exhibited in the information sent on the two channels,
- wherein the processor in a first system is connected to a controller in a second system, said processor incorporating an error checking facility in the information selected by the controller.
Dependencies are inferred from the claim text.