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AssigneeAdtran, Inc.
InventorW. Stuart Venters
Estimating the term…
In a time division multiplexed digital communication network through which time division multiplexed data signals are routed over respectively different transmission paths of the network, the paths having respectively different transmission delays, to a bonding receiver at a destination end of the network, the bonding receiver including a digital signal processor for controlling the operation of the bonding receiver, bonding compensation that is normally carried out entirely by the digital signal processor is transferred from the digital signal processor to an auxiliary delay path, which is coupled to the receive path from the network. The auxiliary delay path is controlled by the direct memory access (DMA) functionality of the digital signal processor to transfer selected data time slots through the auxiliary delay path. The output of the auxiliary delay path is controllably multiplexed with undelayed time slots, so as to be re-injected into the receive path and time division multiplex aligned with and synchronously interleaved with the slower channel's time slots upstream of the input of the digital signal processor.
A bonding delay compensation mechanism for effecting timeslot interleaving alignment of time division multiplexed data signals that have the same transmission rate and have been routed over respectively different transmission paths of a digital communication network at said same transmission rate, which paths have respectively different transmission delays, said bonding delay compensation mechanism comprising a multiplexer coupled in a receive data path from said digital communication network to a bonding receiver, and an auxiliary delay path, which is coupled to said receive data path from said digital communication network and which is controllably operative to delay selected time slots of said time division multiplexed data signals, which are then coupled to said multiplexer, so as to be multiplexed with other time slots of time division multiplexed data signals conveyed over said receive data path, and thereby re-injected into said receive data path and time division multiplex-aligned with and synchronously interleaved with said other time slots of said time division multiplexed data signals upstream of an input to said bonding receiver.
A delay mechanism for imparting a prescribed delay to a digital data stream being transmitted over a digital data communication path, comprising a cascaded arrangement of an input register, a controlled delay unit and an output register, said cascaded arrangement being to coupled said digital data communication path and being controlled by a DMA controller of a digital signal processor, and wherein said input register has an input coupled to said digital data communication path and is operative under DMA control of said DMA controller to temporarily store data bytes associated with successive time slots of said digital data stream, said digital signal processor includes memory, and wherein said DMA controller has a source address counter and a destination address counter, said source address counter pointing to one of said input register and an address in said memory from which data is to be accessed, and wherein said destination address counter points to one of an address in said memory and said output register to which data is to be written.
For use with a time division multiplexed digital communication network through which time division multiplexed data signals are routed over respectively different transmission paths of said digital communication network, which paths have respectively different transmission delays, to a bonding receiver at a destination end of said network, said bonding receiver including a digital signal processor for controlling the operation thereof, a method of effecting timeslot interleaving alignment of time division multiplexed data signals that have been routed over respectively different transmission paths of said digital communication network on a communication path upstream of said bonding receiver comprising the steps of:
For use with a time division multiplexed digital communication network through which time division multiplexed data signals having the same transmission rate are routed over respectively different transmission paths of said digital communication network at said same transmission rate, which paths have respectively different transmission delays, to a bonding receiver at a destination end of said network, said bonding receiver including a digital signal processor for controlling the operation thereof, a method of effecting timeslot interleaving alignment of time division multiplexed data signals that have been routed over respectively different transmission paths of said digital communication network on a communication path upstream of said bonding receiver comprising the steps of:
A delay mechanism for imparting a prescribed delay to digital data stream being transmitted over a digital data communication path, comprising a cascaded arrangement of an input store, an addressable memory and an output store, said cascaded arrangement being coupled to said digital data communication path and being controlled by a DMA controller of a digital signal processor, said DMA controller having a source address counter and a destination address counter, and being operative to selectively access data from one of said input store and an address in said memory in dependence upon a prescribed portion of the contents of said source address counter, and being operative to selectively cause data to be transferred to one of an address in said memory and said output store in dependence upon a prescribed portion of the contents of said destination address counter, and wherein said input store includes an input register coupled to said digital data communication path, and a temporary input holding register coupling said input register to said memory, and wherein said output store includes and output register and a temporary output holding register coupling said memory to said output register, and wherein DMA-controlled data transfers between said input register and said memory are effected through said temporary input holding register, and wherein DMA-controlled data transfers between said memory and said output register are effected through said temporary output holding register.
For use with a time division multiplexed digital communication network through which time division multiplexed data signals having the same transmission frequency are routed over respectively different transmission paths of said digital communication network, which paths have respectively different transmission delays, to a bonding receiver at a destination end of said network, said bonding receiver including a digital signal processor for controlling the operation thereof, a method of effecting timeslot interleaving alignment of time division multiplexed data signals that have been routed over respectively different transmission paths of said digital communication network on a communication path upstream of said bonding receiver comprising the steps of:
A data transfer apparatus comprising a cascaded arrangement of an input store, an addressable memory and an output store, said cascaded arrangement being controlled by a DMA controller of a digital signal processor, said DMA controller having a source address counter, a destination address counter and a temporary store, and being operative to effect a data transfer from said input store to said temporary store in response to the count value stored in said source address counter having a first attribute, to effect a data transfer from said temporary store to that location in said memory specified in said destination address counter in response to the count value stored in said destination address counter having a second attribute, to effect a data transfer from that location in memory specified by said source address counter to said temporary store in response to the count value stored in said source address counter having said second attribute, and to effect a data transfer from said temporary store to said output register in response to the count value stored in said destination register having said first attribute.
A data transfer apparatus comprising a cascaded arrangement of an input store, an addressable memory and an output store, said cascaded arrangement being controlled by a DMA controller of a digital signal processor, said DMA controller having a source address counter, a destination address counter and a temporary store, and being operative to effect a data transfer from said input store to said temporary store during a first DMA-transfer cycle of said DMA controller, to effect a data transfer from said temporary store to that location in said memory specified in said destination address counter during a second DMA-transfer cycle of said DMA controller, to effect a data transfer from that location in memory specified by said source address counter to said temporary store during a third DMA-transfer cycle of said DMA controller, and to effect a data transfer from said temporary store to said output register during a fourth DMA-transfer cycle of said DMA controller.
Dependencies are inferred from the claim text.