Digital signal transmission apparatus

A digital signal processing apparatus, comprising:

• a pair of supervisory circuits for individually supervising a pair of receive signals from a working channel and a protection channel;
• a phase synchronization section for synchronizing the phases of frames and bits of the receive signals from said working channel and said protection channel and outputting the receive signals in a same phase;
• a selector for selectively outputting one of the signals from said phase synchronization section;
• a selector control circuit for selecting, when an abnormal condition detection signal is sent out from one of said supervisory circuits, the receive signal from a normal one of said supervisory circuits to said selector;
• code error detection means provided for each of said working channel and said protection channel for detecting presence or absence of a code error of a virtual container signal in units of a frame using a result of calculation of a bit interleaved parity;
• and
• a frame memory provided for each of said working channel and said protection channel for delaying a signal, for which detection by said code error detection means has been performed, by one frame and outputting the delayed signal to said phase synchronizing section;
• said selector control section including means for switching said selector in units of a frame in response to results of code error detection of a frame by said code error detection means.