Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory

A data transmission circuit for use in a semiconductor integrated circuit comprising:

• a first circuit for converting a first pair of differential signals, each having a first amplitude, to a second pair of differential signals, each having a second amplitude smaller than said first amplitude;
• a pair of signal lines for transmitting the second pair of differential signals obtained through the conversion by said first circuit;
• a second circuit for converting the second pair of differential signals transmitted through said pair of signal lines to a third pair of differential signals, each having a third amplitude;
• and
• a third circuit for latching the third pair of differential signals obtained through the conversion by said second circuit,
• wherein said first pair of differential signals are logic signals, each having a high level and a low level, and the high level of each of said logic signals is equal to a first reduced voltage having been generated inside said semiconductor integrated circuit based on a source voltage supplied from the outside of said semiconductor integrated circuit.

A data transmission circuit for use in a semiconductor integrated circuit comprising:

• a first circuit for converting a first pair of differential signals, each having a first amplitude, to a second pair of differential signals, each having a second amplitude smaller than said first amplitude;
• a pair of signal lines for transmitting the second pair of differential signals obtained through the conversion by said first circuit;
• a second circuit for converting the second pair of differential signals transmitted through said pair of signal lines to a third pair of differential signals, each having a third amplitude;
• and
• a third circuit for latching the third pair of differential signals obtained through the conversion by said second circuit,
• wherein said second pair of differential signals are logic signals, each having a high level and a low level, and the high level of each of said logic signals is equal to a second reduced voltage having been generated inside said semiconductor integrated circuit based on a source voltage supplied from the outside of said semiconductor integrated circuit.

A data transmission circuit for use in a semiconductor integrated circuit comprising:

• a first circuit for converting a first pair of differential signals, each having a first amplitude, to a second pair of differential signals, each having a second amplitude smaller than said first amplitude;
• a pair of signal lines for transmitting the second pair of differential signals obtained through the conversion by said first circuit;
• a second circuit for converting the second pair of differential signals transmitted through said pair of signal lines to a third pair of differential signals, each having a third amplitude;
• and
• a third circuit for latching the third pair of differential signals obtained through the conversion by said second circuit,
• wherein a ground line of said first circuit is provided independently of ground lines of other circuits in said semiconductor integrated circuit.

A data transmission circuit for use in a semiconductor integrated circuit comprising:

• a first circuit for converting a first pair of differential signals, each having a first amplitude, to a second pair of differential signals, each having a second amplitude smaller than said first amplitude;
• a pair of signal lines for transmitting the second pair of differential signals obtained through the conversion by said first circuit;
• a second circuit for converting the second pair of differential signals transmitted through said pair of signal lines to a third pair of differential signals, each having a third amplitude;
• and
• a third circuit for latching the third pair of differential signals obtained through the conversion by said second circuit;
• wherein the operation of said second circuit is halted in synchronization with the latching of said third pair of differential signals by said third circuit.

A data transmission circuit for use in a semiconductor integrated circuit comprising:

• a first circuit for converting a first pair of differential signals, each having a first amplitude, to a second pair of differential signals, each having a second amplitude smaller than said first amplitude;
• a pair of signal lines for transmitting the second pair of differential signals obtained through the conversion by said first circuit;
• a second circuit for converting the second pair of differential signals transmitted through said pair of signal lines to a third pair of differential signals, each having a third amplitude;
• a third circuit for latching the third pair of differential signals obtained through the conversion by said second circuit;
• and
• a fourth circuit for equalizing the potentials of said pair of signal lines.