Method and circuit for timing the loading of nonvolatile-memory output data
AssigneeSGS-Thomson Microelectronics S.A.
InventorsLuigi Pascucci, Marco Maccarrone, Marco Olivo
Life of this patent
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Abstract
A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge of the data simulating signal and enabling supply of the signal to the output simulation circuit and data supply to the output circuits of the memory; a combinatorial network for detecting propagation of the data simulating signal to the output of the output simulation circuit and disabling the data simulating signal; and a reset element for resetting the timing circuit.
Claims18
A method for timing the loading of nonvolatile memory output data, comprising the step of generating a data loading signal for loading data from an internal memory unit into at least one output circuit;
- characterized in that said step of generating a data loading signal comprises steps of:
- generating a data simulating signal;
- simultaneously enabling loading of data into said output circuit and loading of said data simulating signal into an output simulation circuit identical to said output circuit;
- disabling loading of said data simulating signal and said data upon propagation of said data simulating signal to said output simulation circuit;
- and
- resetting said output simulation circuit.
A circuit for timing the loading of nonvolatile memory output data, comprising at least one output circuit;
- said timing circuit generating a load enabling signal;
- characterized in that it comprises an output simulation circuit identical to said output circuit;
- simulating signal generating means for generating a data simulating signal and output-connected to a first input of said output simulation circuit;
- simultaneous enabling means for simultaneously enabling said output simulation circuit and said output circuit;
- and propagation detecting means connected to the output of said output simulation circuit, for resetting said simulating signal generating means.
A method for loading data from a memory unit of a memory circuit into an output circuit of said memory circuit, comprising:
- generating a simulated data signal;
- loading said data into said output circuit and loading said simulated data signal into an output simulation circuit substantially simultaneously, said output simulation circuit and said output circuit having similar delay characteristics;
- and
- ceasing said loading of said data in response to said simulated data signal propagating through said output simulation circuit.
A circuit for controlling the loading of data into an output circuit of a memory device, comprising:
- a data simulator operable to generate a simulated data signal;
- an output simulator operable to receive said simulated data signal and having delay characteristics similar to those of said output circuit;
- an enabler operable to generate an active level of an enable signal in response to said simulated data signal;
- a switching circuit operable to substantially simultaneously couple said data to said output circuit and said simulated data signal to said output simulator in response to said active level;
- and
- a disabler operable to disable said enabler a predetermined time after said simulated data signal propagates through said output simulator.
Dependencies are inferred from the claim text.