DRAM refresh control circuit

Abstract

A control circuit for refreshing a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns. The inventive refresh control circuit includes a first circuit for detecting whether a first refresh mode exists in response to row and column address signals applied thereto and for generating a first output signal based on the result of the detection; a second circuit for detecting whether a second refresh mode exists in response to row and column address signals applied thereto and for generating a second output signal based on the result of the detection; a third circuit for detecting whether a reset condition exists in response to row and column address signals applied thereto and for generating a reset signal based on the result of the detection; and a counter circuit, coupled to the first, second, and third detecting circuits, for generating a count value representing a refresh address in response to the first and second output signals and the reset signal.

Dependencies are inferred from the claim text.