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US 5,515,328 AGranted
Memory circuit with element for the memorizing of word line selection for an erasure of a block of information
AssigneeSGS-Thomson Microelectronics S.A.
InventorGerard Silvestre de Ferron
Life of this patent
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Abstract
In a memory circuit, the word line decoder includes a memorization logic circuit that provides for the memorizing of the selection of the word lines. This memorization provides for the simultaneous erasure of all the words lines for which the selection has been memorized.
Claims32
A memory circuit for an electrically erasable and programmable memory including a word line decoder, said decoder receiving address bits as inputs thereto, and said decoder comprising
- a first logic circuit for obtaining, for each of a plurality of selected word lines, the address bits for the respective selected word line and the logic complements of the address bits for the respective selected word line, wherein said plurality of selected word lines define a block of information, and
- a second logic circuit for decoding said address bits and logic complements to deliver a plurality of word line selection signals, each word line selection signal corresponding to a respective selected word line, and
- a memorization logic circuit connected to receive signals from said second logic circuit and accordingly to memorize information which identifies said block of information for simultaneous erasure of the corresponding word lines.
A method for simultaneously erasing a block of memorized information containing a plurality of word lines in an electrically erasable and programmable memory, comprising the steps of:
- supplying, for each of a plurality of selected word lines, the address bits for the respective selected word line and the logic complements of the address bits for the respective selected word line, wherein said plurality of selected word lines define a block of memorized information containing a plurality of word lines,
- decoding the thus supplied address bits and logic complements to deliver a plurality of word line selection signals, each word line selection signal corresponding to a respective selected word line, and
- memorizing data which identifies the block of memorized information which is to be erased, in response to said decoded address bits accordingly to memorize information which identifies the block of memorized information which is to be erased by a simultaneous erasure of the corresponding word lines.
An integrated circuit memory, comprising:
- address decoder circuitry, connected to receive and decode a plurality of address bits and accordingly to drive a selected one of a plurality of decoded lines into an active state;
- a plurality of memorization circuits, each connected to receive
- a respective one of said decoded address bits,
- a memorization enable signal common to all said memorization circuits, and
- a reset signal common to all said memorization circuits;
- and each
- configured to switch a respective latched output from inactive to active whenever said memorization enable signal goes active while said respective decoded line is active, and
- to switch said respective latched output from active to inactive whenever said reset signal goes active;
- and
- a switch-over logic circuit, connected to receive a mode signal, and said latched outputs from said memorization circuits, and said decoded address bits, accordingly to provide either said latched outputs or said decoded address bits as wordline outputs, in accordance with the state of said mode signal.
7 more elements
An integrated circuit memory, comprising:
- a plurality of memorization circuits,
- each connected to receive
- a respective one of a plurality of true and complemented address bits,
- a memorization enable signal common to all said memorization circuits, and
- a reset signal common to all said memorization circuits;
- and
- each configured
- to provide a respective latched output, to switch said latched output from inactive to active whenever said memorization enable signal goes active while said respective address bit is active, and
- to switch said latched output from active to inactive whenever said reset signal goes active;
- a switch-over logic circuit, connected to receive a mode signal, said latched outputs from said memorization circuits, and said address bits, accordingly to provide either said latched outputs or said address bits as output bits, in accordance with the state of said mode signal;
- and
- address decoder circuitry, connected to receive said output bits from said switch-over logic, accordingly to simultaneously drive all selected ones of a plurality of word lines into an active state.
9 more elements
An integrated circuit memory, comprising:
- an address decoder connected to receive and decode a plurality of address bits and accordingly to drive a selected address line into an active state;
- a plurality of memorization circuits,
- each connected to receive a respective one of said decoded address bits, a memorization enable signal common to all said memorization circuits, and a reset signal common to all said memorization circuits;
- and
- each connected to provide a respective latched output and to switch said latched output from inactive to active whenever said memorization enable signal goes active while said respective decoded is active, and to switch from active to inactive whenever said reset signal goes active;
- and
- switch-over logic connected to receive a mode signal, said latched outputs from said memorization circuits, and said decoded signals, accordingly to provide either said latched outputs or said decoded address bits as wordline outputs, in accordance with the state of said mode signal.
4 more elements
A memory circuit for an electrically erasable and programmable memory including a word line decoder, said decoder receiving address bits as inputs thereto, and said decoder comprising
- a first logic circuit for obtaining, for each of a plurality of selected word lines, the address bits for the respective selected word line and the logic complements of the address bits for the respective selected word line, wherein said plurality of selected word lines define a block of information, and
- a memorization logic circuit connected to receive signals from said first logic circuit and accordingly to memorize information which identifies said block of information for simultaneous erasure of the corresponding word lines and connected to produce an output;
- and
- a second logic circuit connected to decode said address bits and logic compliments and said output of said memorization logic circuit to deliver a plurality of word line selection signals, each word line selection signal corresponding to a respective selected word line.
1 more element
Dependencies are inferred from the claim text.