US 5,515,327 AGranted

Nonvolatile semiconductor memory device having a small number of internal boosting circuits

AssigneeKabushiki Kaisha Toshiba

InventorsNaohiro Matsukawa, Ryouhei Kirisawa, Riichiro Shirota

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Abstract

An EEPROM in which a select transistor to which any memory cell not selected is turned off to inhibit electron injections into the floating gate of the memory cell not selected. The memory cells of the EEPROM are arranged in rows and columns in a substrate. The memory cells forming each column are connected in series. The two endmost memory cells are connected to two select transistors, respectively. The bit lines are connected to a data latch/sense amplifier, which is connected to a column decoder. The column decoder controls the bit lines. A row decoder controls select gates and control gates. A voltage-boosting circuit generates a high voltage, which is applied to the substrate and the select gates to erase data in the EEPROM, and to the control gates to write data into the EEPROM. A low-voltage controller generates a low voltage, which is applied to the select gates for turning off the select transistors of the column not selected, thereby to prevent data-writing.

Claims31

Dependent claims

An electrically erasable programmable nonvolatile memory device comprising:

a semiconductor substrate;
a memory cell unit, including
a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate,
a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and
a control gate electrode provided on said charge-accumulating layer of said transistor;
a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage;
a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor;
charging means for applying, during a first data-writing period when said bit line is not selected, a first voltage to said control gate electrode and said bit line, and a second voltage to said gate electrode of said select transistor to turn on said select transistor, thereby to charge said drain region to a third voltage lower than the second voltage by the threshold voltage of said select transistor;
control-gate voltage switching means for increasing voltages of said source and drain regions and a voltage of a channel region provided between said source and drain regions, thereby to increase the third voltage, by capacitive coupling which occurs between said control gate electrode and said charge-accumulating layer and between said charge-accumulating layer and said source, drain and channel regions when a data-writing high voltage is applied to said control gate during a second data-writing period;
and
data-write prohibiting means for turning off said select transistor to cut off the current path of said memory cell unit when a source-gate voltage of said select transistor falls below the threshold voltage of said select transistor due to the capacitive coupling.

8 more elements

An electrically erasable programmable non-volatile memory device comprising:

a semiconductor substrate;
a memory cell unit, including
a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate,
a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and
a control gate electrode provided on said charge-accumulating layer of said transistor;
a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage;
a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor;
a bit-line charging means for applying, during a data writing period when said bit line is not selected, a first voltage to said bit line, the first voltage being relatively low and higher than the threshold voltage of said select transistor;
a gate-voltage applying means for applying, during the data writing period, a second voltage to said gate electrode of said select transistor, the second voltage being higher than the threshold voltage of said select transistor and not exceeding the first voltage;
and
control-gate voltage switching means for applying a third voltage to said source and drain regions when said memory cell unit is selected, for a predetermined time during the data-writing period, and for applying a high voltage to said control gate after lapse of the predetermined period, the third voltage being lower than the second voltage by at least the threshold voltage of said select transistor.

8 more elements

An electrically erasable programmable nonvolatile memory device comprising:

a semiconductor substrate;
a memory cell unit, including
a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate,
a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and
a control gate electrode provided on said charge-accumulating layer of said transistor;
a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage;
a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor;
charging means for applying, during a first data-writing period when said bit line is not selected, a first voltage to said control gate electrode and said bit line, and a second voltage to said gate electrode of said select transistor to turn on said select transistor, thereby to charge said drain region to a third voltage lower than the second voltage by the threshold voltage of said select transistor;
control-gate voltage switching means for increasing voltages of said source and drain regions and a voltage of a channel region provided between said source and drain regions, thereby to increase the third voltage, by capacitive coupling which occurs between said control gate electrode and said charge-accumulating layer and between said charge-accumulating layer and said source, drain and channel regions when a data-writing high voltage is applied to said control gate during a second data-writing period;
and
data-write prohibiting means for turning off said select transistor to cut off the current path of said memory cell unit when a source-gate voltage of said select transistor falls below the threshold voltage of said select transistor due to the capacitive coupling;
and
verify means for correcting the threshold voltage, the threshold voltage relating to data writing.

10 more elements

An electrically erasable programmable non-volatile memory device comprising:

a semiconductor substrate;
a memory cell unit, including
a plurality of memory cells arranged in series, a first end memory cell having a source region and a second end memory cell having a drain region, said source and drain regions both formed in a surface of said semiconductor substrate,
a transistor having a charge-accumulating layer provided on the surface of said semiconductor substrate, said transistor located between said source and drain regions, and
a control gate electrode provided on said charge-accumulating layer of said transistor;
a select transistor having a gate electrode and a terminal coupled to said drain region of said second end memory cell and having a threshold voltage;
a bit line to which said drain region of said second end memory cell is connected by a current path of said select transistor including said gate electrode and said terminal of said select transistor;
a bit-line charging means for applying, during a data writing period when said bit line is not selected, a first voltage to said bit line, the first voltage being relatively low and higher than the threshold voltage of said select transistor;
a gate-voltage applying means for applying, during the data writing period, a second voltage to said gate electrode of said select transistor, the second voltage being higher than the threshold voltage of said select transistor and not exceeding the first voltage;
and
control-gate voltage switching means for applying a third voltage to said source and drain regions when said memory cell unit is selected, for a predetermined time during the data-writing period, and for applying a high voltage to said control gate after lapse of the predetermined period, the third voltage being lower than the second voltage by at least the threshold voltage of said select transistor;
and
verify means for correcting the threshold voltage, the threshold voltage relating to data writing.

10 more elements

Dependencies are inferred from the claim text.