Synchronous random access memory

A synchronous random access memory, comprising:

• a memory cell array including a plurality of memory cells;
• read/write means responsive to a read/write control signal for reading/writing data from/to a memory cell in said memory cell array selected corresponding to an internal address signal based on an external address signal;
• internal clock generation means responsive to an external clock signal for generating an internal clock signal;
• first logic means responsive to a delay signal of said read/write control signal and said internal clock signal for generating a first logic signal;
• data hold means for fetching data to be written into a memory cell in said memory cell array and holding the data excluding the period during which data is being externally output,
• said data hold means including first latch means responsive to said first logic signal for latching the data to be written in the memory cell in said memory cell array;
• second logic means responsive to said internal clock signal and said read/write control signal for generating a second logic signal;
• address signal hold means for holding an internal address signal corresponding to the data held by said data hold means,
• said address signal hold means including second latch means responsive to said internal clock signal and said read/write control signal for latching the internal address signal corresponding to the data held by said data hold means;
• select means receiving an internal address signal for reading data and the internal address signal held by said address signal hold means and responsive to said read/write control signal for selectively outputting these internal address signals for reading or writing;
• decode means responsive to the internal address signal output from said select means for selecting a memory cell in said memory cell array;
• comparison means for comparing said internal address signal for reading the data and the internal address signal held by said address hold means in order to output data;
• and
• select output means receiving the data held by said data hold means and the data read out by said read/write means and responsive to a result of comparison by said comparison means for selectively outputting these data when data is externally read out.

A synchronous random access memory, comprising:

• a memory cell array including a plurality of memory cells;
• read/write means responsive to a read/write control signal for reading/writing data from/to a memory cell in said memory cell array selected corresponding to an internal address signal based on an external address signal;
• internal clock generation means responsive to an external clock signal for generating an internal clock signal;
• first logic means responsive to a delay signal of said read/write control signal and said internal clock signal for generating a first logic signal;
• data hold means for fetching data to be written into a memory cell in said memory cell array and holding the data excluding the period during which data is being externally output,
• said data hold means including first latch means responsive to said first logic signal for latching the data to be written into the memory cell in said memory cell array;
• second logic means responsive to said internal clock signal and said read/write control signal for generating a second logic signal;
• address signal hold means for holding an internal address signal corresponding to the data held by said data hold means;
• select means receiving an internal address signal for reading out data and the internal address signal held by said address signal hold means and responsive to said read/write control signal for selectively outputting these internal address signals for reading or writing,
• said select means including first multiplexer means for applying said internal address signal for reading the data to said decode means when said read/write control signal designates a reading, while applying the internal address signal held by said address signal hold means to said decode means when said read/write control signal designates a writing;
• decode means responsive to the internal address signal output from said select means for selecting a memory cell in said memory cell array;
• comparison means for comparing said internal address signal for reading the data and said internal address signal held by said address hold means in order to output data;
• select output means receiving the data held by said data hold means and the data read out by said read/write means and responsive to a result of comparison by said comparison means for selectively outputting these data when data is externally read out,
• said select output means including second multiplexer means for outputting the data held by said data hold means when the internal address signals compared by said comparison means coincide and outputting the data read out by said read/write control means when the internal address signals compared by said comparison means do not coincide.

A synchronous random access memory, comprising:

• a memory cell array including a plurality of memory cells;
• read/write means responsive to a read/write control signal for reading/writing data from/to a memory cell in said memory cell array selected corresponding to an internal address signal based on an external address signal;
• data hold means for sequentially fetching a plurality of pieces of data to be written into memory cells in said memory cell array and holding the data in a sequence, excluding the period during which data is being externally output;
• address signal hold means for holding a plurality of internal address signals corresponding to the plurality of pieces of data held by said data hold means in a sequence corresponding to the sequence of these plurality of pieces of data;
• first select means receiving an internal address signal for reading data and the internal address signal which comes first in the sequence of the internal address signals held by said address signal hold means and responsive to said read/write control signal for selectively outputting these internal address signals for reading or writing;
• decode means responsive to the internal address signal output from said first select means for selecting a memory cell in said memory cell array;
• comparison means for comparing said internal address signal for reading the data and the plurality of internal address signals held by said address signal hold means in order to output data;
• second select means receiving the plurality of pieces of data held by said data hold means for selectively outputting these pieces of data based on a result of comparison by said comparison means when data is externally read out;
• and
• select output means receiving the data output from said second select means and the data read out by said read/write means for selectively outputting these pieces of data based on a result of comparison by said comparison means when data is externally read out.