EEPROM having NAND type memory cell array

A nonvolatile semiconductor memory device comprising:

• a memory cell array in which electrically erasable programmable memory cells are arranged in a matrix fashion;
• a plurality of bit lines coupled to said memory cells;
• data circuits for storing write data such data as to set a selected bit line of said plurality of bit lines at one of a first write bit-line voltage or a second write bit-line voltage during a write operation, to control writing conditions of said memory cells in said memory cell array;
• means for detecting at least one defective bit line with a defect of a current leakage after write data have been loaded into said data circuits;
• means for resetting write data corresponding only to said defective bit line among said write data in said data circuits to such data as to set a bit line at one of the first write bit-line voltage or the second bit-line voltage during a write operation;
• and
• means for performing a write operation by controlling the bit line potential for each memory cell in said memory cell array according to the contents of the corresponding data circuit.

A nonvolatile semiconductor memory device comprising:

• a memory cell array in which electrically erasable programmable memory cells are arranged in a matrix fashion and coupled to bit lines;
• a plurality of data circuits for storing data to control writing conditions of said memory cells in said memory array and for sensing the voltages on bit lines of said memory cell array and storing the sensed voltages again;
• means for detecting at least one defective bit line with a defect of a circuit leakage after-data have been loaded into said data circuits;
• means for replacing the contents of said data circuits corresponding only to said defective bit lines with a current leak with such a data item as causes the write operation performing means to set said bit line at the first write bit-line voltage during a write operation, and not changing the contents of the data circuits corresponding to the bit lines with no current leakage when said data circuits sense said voltages on said bit lines and store the sensed voltages again;
• and
• means for performing a write operation by controlling the bit line potential for each memory cell in said memory cell array according to the contents of the corresponding data circuit.