Non-volatile memory circuit for lengthening service life of non-volatile memory devices

A non-volatile memory circuit comprising:

• a memory cell array having electrically programmable non-volatile memory cells;
• a memory peripheral circuit, having a row decoder and a column decoder, for creating an address signal for designating an address in said memory cell array by means of said row decoder and said column decoder according to an external signal to effect the access operation with respect to said memory cell array;
• control signal generation means for generating a first control signal which permits selection of the memory cell involved in the access operation in said memory cell array for a preset period of time in response to a variation of the address signal, and for generating a second control signal having a rise time which lags behind a rise time of the first control signal and a fall time which leads a fall time of the first control signal;
• and
• a latch circuit for latching data read out from the memory cell in an active period of the second control signal;
• wherein all of the memory cells in said memory cell array are set in a non-selected state in a period other than an active period of the first control signal.