Semiconductor memory device equipped with sense amplifiers selectively activated with column address decoded signals

A semiconductor memory device fabricated on a single semiconductor chip, comprising:

• a plurality of addressable memory locations respectively storing data bits readable in the form of potential level, each of said memory locations being implemented by an electrically programmable read only memory cell;
• a first addressing system operative to select memory locations from said plurality of addressable memory locations for reading out the data bits therefrom;
• a plurality of data propagation paths selectively coupled to said plurality of addressable memory cells, and propagating said data bits read out from said memory locations;
• a second addressing system selectively energizing a plurality of selecting signal lines for selecting one of said data bits on said plurality of data propagation paths;
• a plurality of sense amplifiers coupled to said plurality of data propagation paths, respectively, and selectively activated with said plurality of selecting signal lines for rapidly discriminating the potential level of said one of said data bits;
• an output circuit for delivering said one of said data bits to the outside thereof, each of said sense amplifier circuits being implemented by a series combination of a logic gate and a clocked inverter, said logic gate being enabled with an activation signal and coupled with the associated data propagation path, said clocked inverter being enabled with the associated selecting signal line, and output node of said clocked inverter being coupled to the input node of said output circuit;
• a precharging circuit enabled with a precharging signal and having a plurality of precharging transistors gated by said plurality of selecting signal lines for selectively charging said data propagation paths to a predetermined potential level;
• and
• a protection circuit having a plurality of transfer transistors having respective conduction paths inserted in said plurality of data propagation paths, respectively, said plurality of transfer transistors turning on while the data bit stored in one of said memory locations is being accessed, said plurality of transfer transistors turning off while the electrically programmable read only memory cells are being programmed.