Non-volatile memory cell and level shifter

A method of writing to a non-volatile memory cell formed in a semiconductor substrate, said method comprising the steps of:

• providing an array of non-volatile memory cells formed in rows and columns within a semiconductor region, each said cells comprising a source, a drain and a control gate, wherein each of said control gates in a row of said array are coupled to an associated word line and wherein each of said source/drain regions in a column are coupled to an associated bitline;
• holding said semiconductor substrate at a reference voltage potential;
• applying a first voltage to the wordline of a non-volatile memory cell to be written to;
• applying said reference voltage to the wordlines of other non-volatile memory cells in said array;
• applying a second voltage to a bitline of said non-volatile memory cell to be written to, wherein said second voltage is less than said reference voltage potential and wherein the difference between said first voltage and said second voltage is about 18 volts;
• and
• applying said reference voltage to the bitlines of other non-volatile memory cells in said array.

A method of writing to a non-volatile memory cell formed in a semiconductor substrate, said cell comprising a source, a drain and a control gate, said source and drain being formed in a semiconductor region, said semiconductor region being isolated from said substrate said method comprising the steps of:

• holding said semiconductor substrate at a reference voltage potential;
• applying a first voltage to said control gate of said non-volatile memory cell;
• and
• applying a second voltage to said source of said non-volatile memory cell, wherein said second voltage is less than said reference voltage potential and wherein said first voltage has the same magnitude of said second voltage.

A method of writing to a non-volatile memory cell formed in a semiconductor substrate, said cell comprising a source, a drain and a control gate, said source and drain being formed in a semiconductor region, said semiconductor region isolated from said semiconductor substrate, said method comprising the steps of:

• holding said semiconductor substrate at a reference voltage potential;
• applying a first voltage to said control gate of said non-volatile memory cell;
• and
• applying a second voltage to said source of said non-volatile memory cell, wherein said second voltage is less than said reference voltage potential and wherein the difference between said first voltage and said second voltage is about 18 volts.

A method of simultaneously programming a plurality of non-volatile memory cells in an array formed in .a substrate, said method comprising the steps of:

• providing an array of non-volatile memory cells formed in rows and columns within a semiconductor region, said semiconductor region isolated from said substrate, each said cells comprising a source, a drain and a control gate, wherein each of said control gates in a row of said array are coupled to an associated word line and wherein each of said source/drain regions in a column are coupled to an associated bitline;
• holding said substrate at a reference voltage potential;
• applying a first voltage to the wordlines of each of said non-volatile memory cells to be written to;
• and
• applying a second voltage to said bitlines of said non-volatile cells to be written to, said second voltage less than said reference voltage potential and having the same magnitude as said first voltage.

A method of programming a non-volatile memory cell comprising the steps of:

• providing a semiconductor substrate which includes at least one non-volatile memory cell formed therein, said non-volatile memory cell being formed within a semiconductor region which is isolated from said semiconductor substrate, said non-volatile memory cell comprising a source and a drain disposed within said semiconductor and also comprising a control gate;
• applying a positive voltage to said control gate of said non-volatile memory cell;
• applying a negative voltage to said source region of said non-volatile memory cell;
• and
• applying a negative voltage to said semiconductor region.