Dynamic random access memory
AssigneeSony Corporation
InventorsAkihiro Uda, Akihiko Hashiguchi, Akira Nakagawara
Life of this patent
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Abstract
A dynamic random access memory, in which a connection switch circuit is provided between the output of a sense amplifier and a data bus or between memory block, which circuit is controlled in accordance with a write/read control signal of data so as to enable the bit line signal to be read at a high speed and the layout area of the IC to be reduced.
Claims12
A semiconductor memory device in which a transistor having a read gate construction is connected between a bit line and a data bus, comprising:
- a control transistor which is coupled between a drain of the transistor having the read gate construction and a ground;
- a read transistor which is coupled between the transistor having the read gate construction and the data bus and is turned on by a read request signal during a read operation and during a write operation;
- and
- a write transistor which is coupled between the bit line and the transistor having the read gate construction, is turned on by a write request signal, and performs the switching between the bit line and the read transistor,
- wherein said control transistor is turned off during a write operation of data.
A semiconductor memory device wherein two bit lines are respectively segmented into a plurality of parts and connected to a plurality of memory arrays in block, comprising:
- sense amplifiers connected respectively to each of the memory arrays;
- switch means for connecting the bit lines belonging to adjoining memory arrays to each other;
- and
- gate means which are connected in parallel to the switch means with respect to the bit lines,
- wherein each block comprises a pair of said bit line parts corresponding to the two bit lines, respectively.
A semiconductor memory device in which a transistor having a read gate construction is connected between a bit line and a data bus, comprising:
- a control transistor which is coupled between a source of the transistor having the read gate construction and a ground;
- a read transistor which is coupled between the transistor having the read gate construction and the data bus and is turned on by a read request signal during a read operation and during a write operation;
- and
- a write transistor Which is coupled between the bit line and the transistor having the read gate construction, is turned on by a write request signal, and performs the switching between the bit line and the read transistor,
- wherein said control transistor is turned off during a write operation of data.
Dependencies are inferred from the claim text.