US 5,515,311 A · Method of driving ferroelectric memory

Abstract

A ferroelectric memory having a structure in which source and drain are formed on a semiconductor substrate, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a ferroelectric gate transistor memory cell having a ferroelectric gate transistor structure including a gate electrode made of a conductive gate electrode, is arranged on the thin film. An X selection line (column) is connected to the gate of the memory cell, and a Y selection line (row line) is connected to the source and drain, or the column and row of the X and Y selection line are connected to the memory cell vice versa. The memory can be driven only by 1-transistor/1-cell without a pass gate transistor, and the data can be non-destructively read out by applying a voltage lower than the coercive voltage of the ferroelectric to the gate electrode, the source and drain.

Claims18

Dependent claims

A method of driving a ferroelectric memory, wherein the memory comprises a plurality of memory cells arranged in a matrix form, each of said memory cells including a ferroelectric gate transistor, each of said ferroelectric gate transistors including a source and a drain both made of a second conductivity type semiconductor and both formed on a substrate of a first conductivity type semiconductor, a ferroelectric thin film formed between the source and drain, and a conductive gate electrode formed over the ferroelectric thin film, the method comprising the steps of:

arranging said ferroelectric gate transistors of the respective memory cells so as to have only two terminals, one of said two terminals being said gate electrode, and another of said two terminals being one of said source, drain, and a source-drain, and said memory cells being arranged so as to be in a simple matrix;
and
applying a voltage of a predetermined range to said only two terminals of said memory cells so that a voltage applied to a memory cell other than a memory cell selected from said matrix of said memory cells is smaller than a voltage applied the selected cell.

A ferroelectric memory device comprising:

a plurality of memory cells, each of said memory cells including:
(a) a pair of impurity regions formed on a substrate;
(b) a ferroelectric thin film formed on a region located between the impurity regions of said pair of impurity regions;
and
(c) a gate electrode formed on the ferroelectric thin film;
word lines to which gate electrodes of at least some of the memory cells are electrically connected;
first data lines to which one of the pair of impurity regions of each of the memory cells connected to the words lines is connected;
second data lines to which another one of the pair of impurity regions of each of the memory cells connected to the first data lines is connected;
and
switching means for selectively connecting the first add second data lines.

7 more elements

Dependencies are inferred from the claim text.

Method of driving ferroelectric memory

Life of this patent

Method of driving ferroelectric memory

Life of this patent

Abstract

Claims18