US 5,515,309 A · 1-bit adder and multiplier containing a 1-bit adder

Abstract

A one-bit adder includes a carry stage and an adding stage and is constructed in a fast CMOS complementary pass transistor logic with complementary analog CMOS switches in the adding stage which consist of a PMOS and an NMOS transistor. The source of the PMOS transistor is connected with the drain of the NMOS transistor and the drain of the PMOS transistor is connected with the source of the NMOS transistor. The gate of the PMOS transistor receives inverted signals with respect to the gate of the NMOS transistor. Two partial output sum signals are generated by two of the switches which are connected with the input and with the output, respectively, of an inverter and the output sum signal of the adder is available at the output of the inverter. A fast multiplier includes (i) a plurality of the above fast one-bit adders, (ii) reduction of partial products by application of a Booth-McSorley process, (iii) diagonal propagation of caries from one partial product to another allowing all sums on one line to be done simultaneously, and (iv) application of a carry select approach in the final 14 bits and in the first two adders in intermediate rows.

Claims11

Dependent claims

A one-bit adder comprising a carry stage and an adding stage, wherein:

said adding stage of said adder is constructed in a fast CMOS complementary pass transistor logic with complementary analogue CMOS switches which consist of a PMOS and a NMOS transistor;
wherein
the source of said PMOS transistor is connected with the drain of said NMOS transistor and the drain of said PMOS transistor is connected with the source of said NMOS transistor;
the gate of said PMOS transistor receives inverted signals with respect to the gate of said NMOS transistor:
and wherein
two partial output sum signals are generated by two of said switches which are connected with the input and with the output, respectively, of an inverter and wherein
an output sum signal of said adder is available at the output of said inverter (1105).

4 more elements

A digital multiplier with Booth encoding of a multiplier (N0, . . . N11) and diagonal propagation of the carry from one partial product to the other comprising;

a plurality of one bit adders, each comprising a carry stage and an adding stage, said adding stage of said adder being constructed in a fast CMOS complementary pass transistor logic with complementary analog CMOS switches which consist of a PMOS and a NMOS transistor, the source of said PMOS transistor being connected with the drain of said NMOS transistor and the drain of said PMOS transistor being connected with the source of said NMOS transistor, the gate of said PMOS transistor being coupled to receive inverted signals with respect to the gate of said NMOS transistor, wherein two partial output sum signals are generated by two of said switches which are connected with the input and with the output, respectively, of an inverter and wherein an output sum signal of said adder is available at the output of said inverter;
a first row (411) of function blocks (F) which calculate partial products from a multiplicand (401) and from a substring of the multiplier (401) and from a substring of the multiplier (N0, . . . , N11) which has been coded in a Booth encoder circuit (403);
further rows (412, 414, 415, 417, 418) of basic building blocks (FA) which contain one of said function blocks (F) and one of said plurality of one-bit adders (+) and which calculate further partial products from the partial products from the first row or a previous row, respectively, and from further substrings of the multiplier (N0, . . . , N11), which have been coded in further Booth encoder circuits (404, . . . , 408) wherein the respective two or more lowest multiplication results bits (S0, . . . , S9) from each row are calculated using two of said plurality of one-bit adders (+) and wherein groups of such rows (411, 412;
414,415;
417,418) are connected by a pipeline row (413, 416, 419);
and
a last row (410) with a multi-bit carry select adder circuit which is constructed from one-bit adders of said plurality of one-bit adders.

4 more elements

Dependencies are inferred from the claim text.

1-bit adder and multiplier containing a 1-bit adder

Life of this patent

1-bit adder and multiplier containing a 1-bit adder

Life of this patent

Abstract

Claims11