TFT LCD control method for setting display controller in sleep state when no access to VRAM is made

An electronic apparatus, comprising:

• a central processing unit (CPU);
• storage means for storing display data which is read out based on a read timing signal;
• a display device for displaying display data read out from the storage means;
• detecting means for detecting an address specifying a location of the storage means and a memory write signal from the CPU, and for outputting an active signal in response to the detection;
• counter means for counting a predetermined period of time to output a sleep signal, the counter means being reset by receiving the active signal from the detecting means;
• and
• timing signal generating means for generating a read timing signal for the storage means until receiving the sleep signal from the counter means.

An electronic device comprising:

• storage means for storing video data and for outputting the video data in response to a read timing signal;
• a display device for displaying the video data output from the storage means;
• a read timing controller for periodically generating and supplying the read timing signal to the storage means;
• detecting means for detecting whether or not video data is written into the storage means and for outputting a status signal indicating a result of the detection;
• and
• a timer having a counter to count a predetermined period of time and for supplying a sleep signal to the detecting means when the counter counts the predetermined period of time,
• whereby the read timing controller stops supplying the read timing signal upon receiving the sleep signal.

An electronic device, comprising:

• storage means for storing video data and for outputting the video data in response to a read timing signal;
• a display device for displaying the video data output from the storage means;
• detecting means for detecting whether or not the video data is written into the storage means and for outputting a status signal indicating a result of the detection;
• a timer having a counter to count a predetermined period of time, for supplying a sleep signal to read timing controller when the counter counts the predetermined period of time, and for supplying a release signal to the read timing controller when the detecting means detects the write operation;
• and
• read timing controller having an active mode and a sleep mode, the active mode generating and supplying the read timing signal to the storage means periodically, the sleep mode stopping generating the read timing signal to the storage means periodically.

A method for deactivating a display controller in a computer including a counter and a video random access memory (VRAM), wherein the display controller uses a read timing signal to initiate reading of display data from the VRAM, the method performed by the computer comprising the steps of:

• a) detecting an address specifying a location in the VRAM for storing display data;
• b) initializing the counter in response to the detection;
• c) counting a period of time in response to the detection and following the initialization;
• d) generating a sleep signal when the counter reaches a predetermined value;
• e) deactivating the display controller in response to the sleep signal by halting the read timing signal.