US 5,515,024 A · High performance dynamic compare circuit

Abstract

The present invention discloses apparatus and methods for comparing the contents of two digital words and determining whether or not they identically match. The present invention's high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each of the bit compare blocks receives a single bit from a first word A to be compared to a corresponding bit in a second word B. A charge share precharge circuit is coupled to the match line for precharging the match line to a voltage level of V.sub.cc /2. A match feed back circuit is also coupled to the match line and the charge precharge circuit to improve the speed at which the match line is precharged to the voltage level of V.sub.cc /2. A latch is coupled to the match line to electrically latch the state of the match line subsequent to the comparison operation. The comparison circuit of the present invention is dynamic and retains its high speed performance characteristics independent of the word lengths being compared.

Claims14

Dependent claims

A circuit for comparing a first data word and a second data word, each of said data words comprised of a plurality of bits, said circuit comprising:

a match line precharged to a voltage level of V.sub.cc /2;
a plurality of bit compare circuits coupled to said match line in a wired OR configuration, each of said bit compare circuits receiving a bit from said first data word and a corresponding bit from said second data word to compare, each of said bit compare circuits comparing said bits in parallel with one another and providing an output to said match line such that if all of said bits identically match said match line is at a first state, and if any one of said bits do not match said match line is at a second state;
sensing means coupled to said match line to sense the state of said match line to determine if said first and said second words match;
latching means coupled to said match line for latching the state of said match line after the completion of said compare operations by said bit compare circuits.

1 more element

Dependencies are inferred from the claim text.

High performance dynamic compare circuit

Life of this patent

High performance dynamic compare circuit

Life of this patent

Abstract

Claims14