US 5,515,007 A · Triple buffered amplifier output stage

Abstract

In a triple buffer stage output stage applicable to an operational amplifier, the two transistors in the first buffer stage are bootstrapped to the second buffer stage. The collector voltage of each transistor in the first buffer stage thereby follows the input signal at the high impedance node and therefore their parasitic capacitance to the substrate does not have a significant effect. This bootstrapping the collectors of the transistors of the first buffer stage minimizes parasitic capacitance effects and improves phase delay of the output stage. Additionally, the PNP transistors in the signal path of the output stage are fabricated in isolated N-wells to minimize the effect of the N-well to collector capacitance, the N-wells of the signal path PNP transistors which are reverse biased also being bootstrapped. Also provided in the output stage are an RC network connected between the input node of the output stage and its output terminal, and damping resistors to dampen peaking at higher frequencies and minimize temperature effects on amplifier performance. In a second embodiment, the two transistors in the first buffer stage each has multiple additional emitters, each connected to the output terminal. This bootstraps the output stage at lower frequencies, improving performance.

Claims25

Dependent claims

An output stage for an amplifier comprising:

an input node;
a first buffer stage having a first transistor and a second transistor, each of the first and second transistors having a control terminal connected to the input node;
a second buffer stage having a first transistor and a second transistor, the first transistor of the second buffer stage having a control terminal connected to a first current handling terminal of the first transistor of the first buffer stage, and the second transistor of the second buffer stage having a control terminal connected to a first current handling terminal of the second transistor of the first buffer stage;
a third buffer stage having a first transistor and a second transistor, a control terminal of the first transistor being connected to a first current handling terminal of the first transistor of the second buffer stage, and a control terminal of the second transistor of the third buffer stage being connected to a first current handling terminal of the second transistor of the second buffer stage;
wherein a second current handling terminal of the first transistor of the first buffer stage is connected to the first current handling terminal of the second transistor of the second buffer stage and to the control terminal of the second transistor of the third buffer stage, and a second current handling terminal of the second transistor of the first buffer stage is connected to the first current handling terminal of the second transistor of the second buffer stage and to the control terminal of the first transistor of the third buffer stage;
wherein the first transistor of each buffer stage is of a first polarity type and the second transistor of each buffer stage is of a second polarity type;
and
an output terminal connected to the first current handling terminal of both the first and second transistors of the third buffer stage.

5 more elements

An output stage for an amplifier comprising:

an input node;
a first buffer stage having a first transistor and a second transistor, each of the first and second transistors having a control terminal connected to the input node, wherein each of the first and second transistors in the first buffer stage is reverse biased;
a first current source connected to the first current handling terminal of the first transistor of the first buffer stage, and a second current source connected to the first current handlinch terminal of the second transistor of the first buffer stage;
a second buffer stage having a first transistor and a second transistor, the first transistor of the second buffer stage having a control terminal connected to a first current handling terminal of the first transistor of the first buffer stage, and the second transistor of the second buffer stage having a control terminal connected to a first current handling terminal of the second transistor of the first buffer stage;
a third buffer stage having a first transistor and a second transistor, a control terminal of the first transistor being connected to a first current handling terminal of the first transistor of the second buffer stage, and a control terminal of the second transistor of the third buffer stage being connected to a first current handling terminal of the second transistor of the second buffer stage;
wherein a second current handling terminal of the first transistor of the first buffer stage is connected to the first current handling terminal of the second transistor of the second buffer stage, and a second current handling terminal of the second transistor of the first buffer stage is connected to the first current handling terminal of the second transistor of the second buffer stage;
wherein the first transistor of each buffer stage is of a first polarity type and the second transistor of each buffer stage is of a second polarity type;
and
an output terminal connected to the first current handling terminal of both the first and second transistors of the third buffer stage.

6 more elements

An output stage for an amplifier comprising:

an input node;
a first buffer stage having a first transistor and s second transistor, each of the first and second transistors having a control terminal connected to the input node;
a second buffer stage having a first transistor and s second transistor, the first transistor of the second buffer stage having a control terminal connected to a first current handling terminal of the first transistor of the first buffer stage, and the second transistor of the second buffer stage having a control terminal connected to a first current handling terminal of the second transistor of the first buffer stage;
a third buffer stage having a first transistor and a second transistor, a control terminal of the first transistor being connected to a first current handling terminal of the first transistor of the second buffer stage, and a control terminal of the second transistor of the third buffer stage being connected to a first current handling terminal of the second transistor of the second buffer stage;
wherein a second current handling terminal of the first transistor of the first buffer stage is connected to the first current handling terminal of the second transistor of the second buffer stage, and a second current handling terminal of the second transistor of the first buffer stage is connected to the first current handling terminal of the second transistor of the second buffer stage;
wherein the first transistor of each buffer stage is of a first polarity type and the second transistor of each buffer stage is of a second polarity type;
an output terminal connected to the first current handling terminal of both the first and second transistors of the third buffer stage;
and
a shorting circuit connected to the output terminal and to the third buffer stage, the shorting circuit including a first and a second transistor each having a first current handling terminal connected to the output terminal, and each having a control terminal connected respectively to the first current handling terminals of respectively the first and second transistors of the third buffer stage.

6 more elements

Dependencies are inferred from the claim text.

Triple buffered amplifier output stage

Life of this patent

Triple buffered amplifier output stage

Life of this patent

Abstract

Claims25