Differential switched capacitor circuit
AssigneeMotorola, Inc.
InventorsVladimir Koifman, Yachin Afek
Life of this patent
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Abstract
A differential switched capacitor circuit (6) for sampling a differential input signal (IP, IM) in different sampling phases (PHI0, PHI1) and for correcting errors at an output thereof, comprises: m switched capacitor stages (8-16) coupled in a chain, a first stage (8) being coupled to the output of the circuit, each of the m switched capacitor stages (8-16) being coupled to an adjacent stage in the chain depending on the sampling phase such that a charge representative of the error is equally shared between adjacent stages in the chain and wherein the mth stage (16) is selectively coupled to an end node so as to cancel the charge thereon, whereby after a number of sampling phases the error at the output is substantially reduced by a factor of up to 1/m.
Claims16
A differential switched capacitor circuit for sampling a differential input signal in different sampling phases and for correcting errors at an output thereof, the circuit comprising:
- m switched capacitor stages coupled in a chain, a first stage being coupled to the output of the circuit, and wherein the m capacitor stages comprise at least one first type of stage and at least one second type of stage, the stages being arranged such that an adjacent stage in the chain is a different type, and wherein each type of stage comprises first and second capacitors, first and second inputs selectively coupled to receive the differential input signal, third and fourth inputs and first and second outputs for selectively coupling to the third and fourth inputs of the first stage, the first and second outputs of the mth stage or the third and fourth inputs or first and second outputs of an adjacent stage depending on the sampling phase such that a charge representative of the error is equally shared between adjacent stages in the chain, the mth stage being selectively coupled to an end node so as to cancel the charge thereon,
- wherein during a first sampling phase, the first capacitor of the first type of stage is coupled between the first input and the third input and the second capacitor of the first type is coupled between the second input and the fourth input and the first capacitor of the second type of stage is coupled between the second input and the first output and the second capacitor of the second type is coupled between the first input and the second output,
- wherein during a second sampling phase, the first capacitor of the first type is coupled between a first node and the first output and the second capacitor of the first type is coupled between the first node and the second output, and the first capacitor of the second type is coupled between a second node and the third input and the second capacitor of the second type is coupled between the second node and the fourth input, whereby after a number of first and second sampling phases the error at the output is substantially reduced by a factor of up to 1/m.
A differential switched capacitor circuit for sampling a differential input signal in different sampling phases and for correcting errors at an output thereof, the circuit comprising:
- m switched capacitor stages coupled in a chain, a first stage being coupled to the output of the circuit, and wherein the m capacitor stages comprise at least one first type of stage and at least one second type of stage, the stages being arranged such that an adjacent stage in the chain is a different type, and wherein each type of stage comprises first and second capacitors, first and second inputs selectively coupled to receive the differential input signal, third and fourth inputs and first and second outputs for selectively coupling to the third and fourth inputs of the first stage, the first and second outputs of the mth stage or the third and fourth inputs or first and second outputs of an adjacent stage depending on the sampling phase such that a charge representative of the error is equally shared between adjacent stages in the chain, the mth stage being selectively coupled to an end node so as to cancel the charge thereon,
- wherein during a first sampling phase, the first capacitor of the first type of stage is coupled between the first input and the third input and the second capacitor of the first type is coupled between the second input and the fourth input and the first capacitor of the second type of stage is coupled between the second input and the first output and the second capacitor of the second type is coupled between the first input and the second output,
- wherein during a second sampling phase, the first capacitor of the first type is coupled to the second capacitor and the first output and the second capacitor of the first type is coupled to the first capacitor and the second output, and the first capacitor of the second type is coupled to the second capacitor and the third input and the second capacitor of the second type is coupled to the first capacitor and the fourth input, whereby after a number of first and second sampling phases the error at the output is substantially reduced by a factor of up to 1/m.
Dependencies are inferred from the claim text.