US 5,514,997 AGranted

Inverting delay circuit

AssigneeU.S. Philips Corporation

InventorPatrick J. Quinn

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Abstract

An inverting delay circuit including a differential amplifier (OTA) having a non-inverting input (+) coupled to ground, an inverting input (-) and an output; an input capacitor (Cin) which is coupled between an input of the inverting delay circuit and the inverting input (-) during a first switching phase (.phi.), and which is discharged during a second switching phase (); a feedback capacitor (Cx) which is coupled between the output and the inverting input (-) of the differential amplifier (OTA) during the first switching phase (.phi.), and between the inverting input (-) and ground during the second switching phase (); and an output capacitor (Co) which is coupled between the output and the inverting input (-) during the second switching phase (), the output capacitor (Co) being discharged during the first switching phase (.phi.), a charge on the feedback capacitor (Cx) being transferred to the output capacitor (Co) during the second switching phase ().

Claims8

Dependent claims

An inverting delay circuit comprising:

differential amplifying means (OTA) having non-inverting input means (+) coupled to ground, inverting input means (-) and output means;
input capacitor means (Cin) which are coupled between an input of said inverting delay circuit and said inverting input means (-) during a first switching phase (.phi., 1), said input capacitor means (Cin) being discharged during another switching phase (), 4);
feedback capacitor means (Cx) which are coupled between said output means and said inverting input means (-) during said first switching phase (.phi., 1), said feedback capacitor means (Cx) being coupled between said inverting input means (-) and ground during a second switching phase (, 2), wherein said feedback capacitor means does not affect a transfer function of said inverting delay circuit;
and
output capacitor means (Co) which are coupled between said output means and said inverting input means (-) during said second switching phase (, 2), said output capacitor means (Co) being discharged during said first switching phase (.phi., 1), a charge on said feedback capacitor means (Cx) being transferred to said output capacitor means (Co) during said second switching phase (, 2).

2 more elements

An inverting delay circuit comprising:

differential amplifying means having non-inverting input means coupled to ground, inverting input means and output means;
input capacitor means having a first terminal means and a second terminal means;
first switching means for coupling the first terminal means of said input capacitor means to an input of said inverting delay circuit, and the second terminal means of said input capacitor means to said inverting input means during a first switching phase;
second switching means coupled to the first and second terminal means of said input capacitor means for discharging said input capacitor means during another switching phase;
feedback capacitor means having first terminal means and second terminal means;
third switching means for coupling the first terminal means of said feedback capacitor means to the output means of said differential amplifying means during said first switching phase;
fourth switching means for coupling the first terminal means of said feedback capacitor means to ground during a second switching phase;
means for coupling the second terminal means of said feedback capacitor means to the inverting input means of said differential amplifying means during said first and second switching phases;
output capacitor means having first terminal means and second terminal means;
fifth switching means coupled to the first and second terminal means of said output capacitor means for discharging said output capacitor means during said first switching phase;
and
sixth switching means for coupling the first terminal means of said output capacitor means to said inverting input means and the second terminal means of said output capacitor means to said output means of said differential amplifying means during said second switching means;
whereby said input capacitor means is discharged during said second switching phase, said output capacitor means is discharged during said first switching phase, and said feedback capacitor means does not affect a transfer function of the inverting delay circuit.

10 more elements

Dependencies are inferred from the claim text.