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US 5,514,994 AGranted
Bootstrap circuit
AssigneeNippon Steel Corporation
InventorKikuzo Sawada
Life of this patent
Estimating the term…
Abstract
A bootstrap circuit particularly suitable for low voltage applications and use with semiconductor memories is disclosed.
Claims16
A bootstrap circuit comprising:
- a first enhancement N-channel MOS (Metal Oxide Semiconductor) transistor having a drain connected to an input terminal of the bootstrap circuit and a source connected to an output terminal of the bootstrap circuit;
- a first enhancement P-channel MOS transistor having a gate connected via a first inverter to the source of said first enhancement N-channel MOS transistor and a drain connected to a power source terminal;
- a first capacitor having one terminal connected to a source of said first enhancement P-channel MOS transistor and the other terminal connected to the source of said first enhancement N-channel MOS transistor;
- a second enhancement N-channel MOS transistor having a drain connected to the source of said first enhancement P-channel MOS transistor, a source connected to a ground terminal, and a gate connected via a second inverter to said input terminal;
- a second capacitor having one terminal connected to an input terminal of said second inverter and the other terminal connected to the ground terminal;
- and
- gate potential controlling means for controlling a gate potential of said first enhancement N-channel MOS transistor so as to raise the gate potential to a power source potential or higher during a predetermined time period immediately after an input signal applied to said input terminal rises and to maintain the gate potential to be substantially the same as the power source potential during a time period other than said predetermined time period.
4 more elements
A bootstrap circuit comprising:
- an input terminal to which an input signal to the bootstrap circuit is applied;
- an output terminal of the bootstrap circuit;
- a power source terminal to which a power source voltage is supplied;
- a ground terminal;
- a first enhancement N-channel MOS (Metal Oxide Semiconductor) transistor having a drain connected to said input terminal and a source connected to said output terminal;
- a first inverter having an input port connected to the source of said first enhancement N-channel MOS transistor;
- a first enhancement P-channel MOS transistor having a gate connected to an output port of said first inverter and a drain connected to said power source terminal:
- a first capacitor having one terminal connected to the source of said first enhancement P-channel MOS transistor and having the other terminal connected to the source of said first enhancement N-channel MOS transistor;
- a second enhancement N-channel MOS transistor having a drain connected to the source of said first enhancement P-channel MOS transistor and a source connected to said ground terminal;
- a delay circuit for delaying said input signal, said delay circuit being connected between said input terminal and a gate of said second enhancement N-channel MOS transistor;
- and
- gate potential controlling means for controlling a gate potential of said first enhancement N-channel MOS transistor, by using said input signal and said input signal delayed by said delay circuit, so as to raise the gate potential to said power source voltage or higher during a predetermined time period immediately after said input signal rises and to maintain the gate potential to be substantially the same as said power source voltage during a time period other than said predetermined time period.
9 more elements
Dependencies are inferred from the claim text.