US 5,514,990 AGranted

Frequency multiplier circuit

AssigneeKabushiki Kaisha Toshiba

InventorsKiyoshi Mukaine, Ayako Hirata, Kazuhiko Kasai

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Abstract

An input buffer circuit includes an output circuit and supplies a plurality of signals in response to an input signal. A delay line is constituted of a plurality of delay cells connected in series and delays the signals supplied from the input buffer circuit. A PLL circuit connected to the delay line, includes a level converter which outputs a control signal for controlling a delay time of the delay line. An output signal generation circuit generates a signal having a multiplied frequency from the output signal of the input buffer circuit and the output signal of a tap of the delay line. Each of the delay cells has an output circuit having the same arrangement as that of the output circuit provided in the input buffer circuit, and a clocked inverter circuit included in each of the output circuits of the delay cells and input buffer circuit is controlled by the control signal output from the level converter. Therefore, the waveform of the signal output from the output circuit of the input buffer circuit can be made identical with that of the signal output from the output circuit of each delay cell, and the signal having the multiplied frequency output from the output signal generation circuit has a fixed duty ratio.

Claims3

Dependent claims

A multiplier circuit comprising:

an input circuit supplied with an input signal, said input circuit including a first output circuit for outputting first to third signals in response to the input signal;
a delay circuit having a plurality of delay cells each having a second output circuit, each of said delay cells delaying the first signal supplied from said input circuit for a predetermined time, and outputting a signal from said second output circuit;
a phase comparator circuit connected to said input circuit and said delay circuit, for comparing a phase of the signal output from said delay circuit and a phase of the second signal output from said input circuit thereby to output a voltage corresponding to a difference in phase between the signals;
a level converter circuit connected to said phase comparator circuit, for converting a level of the voltage output from said phase comparator and generating a control signal for controlling a delay time of each of said delay cells;
and
an output signal generation circuit connected to said input circuit and at least one tap of said delay circuit, for generating a signal having a multiplied frequency from a signal output from said at least one tap of said delay circuit and the third signal output from said input circuit,
said first and second output circuits each including a clocked inverter circuit controlled by the control signal generated from said level converter circuit.

4 more elements

A multiplier circuit comprising:

an input circuit supplied with an input signal, said input circuit including a first output circuit for outputting first to third signals in response to the input signal;
a delay circuit having a plurality of delay cells each having a second output circuit, each of said delay cells delaying the first signal supplied from said input circuit for a predetermined time, and outputting a signal from said second output circuit;
a phase comparator circuit connected to said input circuit and said delay circuit, for comparing a phase of the signal output from said delay circuit and a phase of the second signal output from said input circuit thereby to output a voltage corresponding to a difference in phase between the signals;
a level converter circuit connected to said phase comparator circuit, for converting a level of the voltage output from said phase comparator and generating first and second control signals for controlling a delay time of each of said delay cells;
an output signal generation circuit connected to said input circuit and at least one tap of said delay circuit, for generating a signal having a multiplied frequency from a signal output from said at least one tap of said delay circuit and the third signal output from said input circuit;
and
a clocked inverter circuit included in each of said first and second output circuits,
said clocked inverter circuit including:
first and second transistors having gates connected to each other and drains connected to each other, the gates of said first and second transistors receiving the input signal, and the drains thereof supplying an output signal;
a third transistor having a current path connected between a source of said first transistor and a first power supply and a gate supplied with the first control signal from said level converter circuit;
and
a fourth transistor having a current path connected between a source of said second transistor and a second power supply and a gate supplied with the second control signal from said level converter circuit.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/363,323Filed 23 Dec 1994
Priority: JP 5-34723227 Dec 1993
Granted: 7 May 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03L 7/16
Using a reference signal applied to a frequency- or phase-locked loop: indirect frequency synthesis, i.e. generating a desired one of a number of…
H03K 5/00006
Manipulating of pulses not covered by one of the other main groups of this subclass: changing the frequency
H03L 7/0816
And where no voltage or current controlled oscillator is used: the controlled phase shifter and the frequency- or phase-detection arrangement…
H03B 19/00
Generation of oscillations by non-regenerative frequency multiplication or division of a signal