US 5,514,986 AGranted

Sense circuit, memory circuit, negative-resistance circuit, schmitt trigger, load circuit, level shifter, and amplifier

AssigneeOki Electric Industry Co., Ltd.

InventorSatoru Tanoi

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Abstract

A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Claims9

Dependent claims

A memory circuit, comprising:

a first data bus line;
a first resistance circuit coupled between said first data bus line and a fixed potential;
a second data bus line;
a second resistance circuit coupled between said second data bus line and said fixed potential;
and
a plurality of sense circuits for generating differential voltage signals on said first data bus line and said second data bus line, each sense circuit having, respectively:
a first input terminal;
a second input terminal;
a first output terminal coupled to said first data bus line;
a second output terminal coupled to said second data bus line;
an enable terminal for receiving an enable signal;
a first depletion-mode field-effect transistor having a source coupled to said first input terminal, a gate coupled to said second input terminal, and a drain;
a first enhancement-mode field-effect transistor coupled in series between the drain of said first depletion-mode field-effect transistor and said first output terminal;
with a gate coupled to said enable terminal;
a second depletion-mode field-effect transistor having a source coupled to said second input terminal, a gate coupled to said first input terminal, and a drain coupled to said second output terminal;
and
a second enhancement-mode field-effect transistor coupled in series between the drain of said second depletion-mode field-effect transistor and said second output terminal, with a gate coupled to said enable terminal.

14 more elements

A memory circuit powered by a first fixed potential, comprising:

a first data bus line;
first resistance circuit coupled between said first data bus line and said first fixed potential;
a second data bus line;
a second resistance circuit coupled between said second data bus line and said first fixed potential;
and
a plurality of sense circuits for generating differential voltage signals on said first data bus line and said second data bus line, each sense circuit having, respectively:
a first input terminal;
a second input terminal;
a first output terminal coupled to said first data bus line;
a second output terminal coupled to said second data bus line;
an enable terminal for receiving an enable signal;
a first negative-resistance circuit coupled to provide a variable negative resistance between said first input terminal and said first output terminal, responsive to a potential of said second input terminal;
a first enhancement-mode field-effect transistor coupled in series between said first negative-resistance circuit and said first output terminal, with a gate coupled to said enable terminal;
a second negative-resistance circuit coupled to provide a variable negative resistance between said second input terminal and said second output terminal, responsive to a potential of said first input terminal;
and
a second enhancement-mode field-effect transistor coupled in series between said second negative-resistance circuit and said second output terminal, with a gate coupled to said enable terminal.

13 more elements

Dependencies are inferred from the claim text.