Methods and apparatus for dynamically reducing ringing of driver output signal

A driver circuit comprising:

• (a) a driver having an input for receiving an input signal (VIN) and an output for providing an output signal (OUTPUT) to a bus terminated with a terminating voltage (VT);
• and
• (b) clamp means, coupled to said driver, for receiving a clamp gate signal (CLAMP GATE) and sinking current from said output signal during a period when said output signal is in a first prescribed state and said clamp gate signal is in a second prescribed state;
• wherein said first and second prescribed states are HIGH.

A driver circuit comprising:

• (a) a driver having an input for receiving an input signal (VIN) and an output for providing an output signal (OUTPUT) to a bus terminated with a terminating voltage (VT);
• and
• (b) clamp means, coupled to said driver, for receiving a clamp gate signal (CLAMP GATE) and sinking current from said output signal during a period when said output signal is in a first prescribed state and said clamp gate signal is in a second prescribed state;
• wherein said driver comprises a pre-driver stage;
• a driver stage comprising a plurality of parallel transistor devices having gates that receive a DRIVER GATE signal from the pre-driver stage and drains that provide a OUTPUT signal.

A driver circuit comprising:

• (a) a driver having an input for receiving an input signal (VIN) and an output for providing an output signal (OUTPUT) to a bus terminated with a terminating voltage (VT);
• and
• (b) clamp means, coupled to said driver, for receiving a clamp gate signal (CLAMP GATE) and sinking current from said output signal during a period when said output signal is in a first prescribed state and said clamp gate signal is in a second prescribed state;
• wherein said clamp means comprises a first arrangement of plural parallel transistor devices having drain terminals and gates terminals tied to said drain terminals;
• and a second arrangement of plural parallel transistor devices having grounded source terminals, drain terminals connected to source terminals of the devices of said first arrangement, and gates that receive the CLAMP GATE signal to enable the clamp means.

A driver circuit comprising:

• (a) a driver having an input for receiving an input signal (VIN) and an output for providing an output signal (OUTPUT) to a bus terminated with a terminating voltage (VT);
• and
• (b) clamp means, coupled to said driver, for receiving a clamp gate signal (CLAMP GATE) and sinking current from said output signal during a period when said output signal is in a first prescribed state and said clamp gate signal is in a second prescribed state;
• wherein said delay circuit comprises at least two inverters.

A driver circuit comprising:

• (a) a driver having an input for receiving an input signal (VIN) and an output for providing an output signal (OUTPUT) to a bus terminated with a terminating voltage (VT);
• (b) clamp means, coupled to said driver, for receiving a clamp gate signal (CLAMP GATE) and sinking current from said output signal during a period when said output signal is in a first prescribed state and said clamp gate signal is in a second prescribed state;
• and
• a delay circuit, coupled to said driver and said clamp means, for disabling said clamp means after a prescribed delay following a transition of said output signal (OUTPUT) to said first prescribed state;
• wherein said clamp gate signal is derived from a driver gate signal (DRIVER GATE) provided by said driver;
• wherein said delay circuit receives and delays said driver gate signal, and provides said driver gate signal to said clamp means as said clamp gate signal;
• wherein said driver comprises a pre-driver stage;
• a driver stage comprising a plurality of parallel transistor devices having gates that receive the DRIVER GATE signal from the pre-driver stage and drains that provide a OUTPUT signal;
• wherein said clamp means comprises a first arrangement of plural parallel transistor devices having drain terminals and gates terminals tied to said drain terminals;
• and a second arrangement of plural parallel transistor devices having grounded source terminals, drain terminals connected to source terminals of the devices of said first arrangement, and gates that receive the CLAMP GATE signal to enable the clamp means;
• and
• wherein said delay circuit comprises at least two inverters.