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US 5,514,905 AGranted
Semiconductor device
AssigneeHitachi, Ltd.
InventorsToshiyuki Sakuta, Kazuyuki Miyazawa, Satoshi Oguchi, Aizo Kaneda, Masao Mitani, Shozo Nakamura, Kunihiko Nishi, Gen Murakami
Life of this patent
Estimating the term…
Abstract
A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.
Claims18
A semiconductor memory device comprising:
- a rectangular-shaped semiconductor chip having a main surface;
- a plurality of electrodes arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row;
- first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed electrodes so that the arrayed electrodes are interposed between said first and second memory cell array regions;
- first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed electrodes, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed electrodes;
- a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface, and said plurality of leads being electrically connected to said plurality of electrodes, respectively;
- and
- a resin for molding said semiconductor chip and the inner lead portions of said plurality of leads.
4 more elements
A semiconductor memory device comprising:
- a rectangular-shaped semiconductor chip having a main surface;
- a plurality of electrodes arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row;
- first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed electrodes so that the arrayed electrodes are interposed between said first and second memory cell array regions;
- first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed electrodes, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed electrodes;
- a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface;
- means for electrically connecting the end portions of said plurality of leads with associated ones of said plurality of electrodes, respectively;
- and
- a resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and the electrically connecting means.
5 more elements
A semiconductor memory device comprising:
- a rectangular-shaped semiconductor chip having a main surface;
- a plurality of bonding pads arranged at a central area of said main surface of said semiconductor chip and arrayed substantially in at least one row;
- first and second memory cell array regions arranged apart from each other at said main surface of said semiconductor chip, each of said first and second memory cell array regions extending along the arrayed bonding pads so that the arrayed bonding pads are interposed between said first and second memory cell array regions;
- first and second peripheral circuit regions arranged apart from each other at said main surface of said semiconductor chip, said first peripheral circuit region being arranged between said first memory cell array region and the arrayed bonding pads, and said second peripheral circuit region being arranged between said second memory cell array region and the arrayed bonding pads;
- a plurality of leads, wherein each lead has an inner lead portion and an outer lead portion extending outwardly from said inner lead portion, said inner lead portion having an end portion of said lead which overlies said main surface,
- a plurality of wires each of which electrically connecting said end portion of a respective lead with an associated one of said plurality of bonding pads;
- and
- a resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said plurality of wires.
5 more elements
Dependencies are inferred from the claim text.